| поискавой системы для электроныых деталей |
|
LM9040 датащи(PDF) 6 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
LM9040 датащи(HTML) 6 Page - National Semiconductor (TI) |
|
6 / 10 page ![]() Common Mode Filtering (Continued) For a common mode sine wave signal having a frequency 100 Hz and with a FCLOCK of 100 kHz the minimum com- mon mode rejection would be CMRR e 2 314159 100 5E-6 453 CMRR e 0014 eb37 dB If the common mode sine wave has a peak to peak value of 2V the maximum voltage error at the output would be VOUT(CM) e 2V 0014 e 28 mV As this formula shows the value of VOUT(CM) is proportional to the frequency of the CMR signal If the frequency is dou- bled the value of VOUT(CM) is also doubled The addition of a small bypass capacitor (CCM) from the non-inverting input to ground will help counter this problem See Figure 6 How- ever the use of this bypass capacitor creates a new prob- lem in that the differential input is no longer balanced While the Lambda sensor is cold (ie RSENSOR l 10 MegX) there is little difference in CMR performance As the Lambda sen- sor heats to the operating temperature and the sensor re- sistance decreases the common mode signal is no longer applied to both inputs equally This imbalance causes VOUT(CM) to increase as RSENSOR decreases as the non- inverting input will see the full common mode signal while the non-inverting input will see an attenuated common mode signal The selection of the value of the CMR bypass capacitor needs to be balanced with the need for reasonable reduc- tion or elimination of common mode signals with both cold and hot sensors Since normal operation will need to in- clude consideration of the entire impedance range of the sensor a trade off in overall application performance may be needed Generally the value of the CMR bypass capacitor should be kept as low as possible and should not be larger than the differential input filter capacitor Values in the range of 0001 mF to 001 mF will usually provide reasonable CMR results but optimum results will need to be determined em- pirically as the source of common mode signals will be unique to each application Gain and Filter Stage The signal gain and filter stage is designed to have a DC gain of 453 VV with a cut-off frequency of typically 500 Hz The external 4 kX resistors on each input pin are in series with the differential input impedance Together they form a voltage divider circuit across the input such that the net DC gain of the application circuit is 450 VV TLH12372 – 17 FIGURE 7 Simplified Gain and Filter Circuit The internal gain is set by the ratio of CIN and CFB GAINDC e CIN CFB GAINDC e 74213 pF 16383 pF e 453 VV The corner frequency (b3 dB) is set by the ratio of CFB and CINT and by FCLOCK FC e FCLOCK CFB 2 q CINT FC e 1E5 16383E-12 2 314159 521E-12 e 500 Hz TLH12372 – 18 FIGURE 8 Equivalent Gain and Filter Circuit 6 |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |