DS2196L datasheet(40/157 Pages) DALLAS

40 / 157 page

DS2196

40 of 157

CCR2A: COMMON CONTROL REGISTER 2 FRAMER A (Address = 38 Hex)

(MSB)

(LSB)

TFM

TB8ZS

TSLC96

TZSE

RFM

RB8ZS

RSLC96

RFDL

SYMBOL

POSITION

NAME AND DESCRIPTION

TFM

CCR2A.7

Transmit Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

TB8ZS

CCR2A.6

Transmit B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

TSLC96

CCR2A.5

Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this

bit to a 1 in D4 framing applications. Must be set to 1 to source

the Fs pattern. See Section 18 for details.

0 = SLC–96/Fs–bit insertion disabled

1 = SLC–96/Fs–bit insertion enabled

TZSE

CCR2A.4

Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using

the internal HDLC/BOC controller instead of the legacy support

for the FDL. See Section 18 for details.

0 = zero stuffer disabled

1 = zero stuffer enabled

RFM

CCR2A.3

Receive Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

RB8ZS

CCR2A.2

Receive B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

RSLC96

CCR2A.1

Receive SLC–96 Enable. Only set this bit to a 1 in D4/SLC–

96 framing applications. See Section 18 for details.

0 = SLC–96 disabled

1 = SLC–96 enabled

RFDL

CCR2A.0

Receive FDL Zero Destuffer Enable. Set this bit to 0 if using

the internal HDLC/BOC controller instead of the legacy support

for the FDL. See Section 18 for details.

0 = zero destuffer disabled

1 = zero destuffer enabled

DS2196L датащи(PDF) 40 Page - Dallas Semiconductor

DS2196L датащи(HTML) 40 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL