X9421 datasheet(6/21 Pages) XICOR

6 / 21 page

X9421

REV 1.1.6 8/1/02

Characteristics subject to change without notice.

6 of 21

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Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW

to HIGH after a complete write sequence is received by

the device. The progress of this internal write operation

can be monitored by a Write In Process bit (WIP). The

WIP bit is read with a Read Status command.

INSTRUCTIONS

Address/Identification (ID) Byte

The ﬁrst byte sent to the X9421 from the host, following

a CS going HIGH to LOW, is called the Address or

Identiﬁcation byte. The most signiﬁcant four bits of the

slave address are a device type identiﬁer, for the

X9421 this is ﬁxed as 0101[B] (refer to Figure 2).

The least signiﬁcant bit in the ID byte selects one of

two devices on the bus. The physical device address is

deﬁned by the state of the A0 input pin. The X9421

compares the serial data stream with the address input

state; a successful compare of the address bit is

required for the X9421 to successfully continue the

command sequence. The A0 input can be actively

driven by a CMOS input signal or tied to VCC or VSS.

The remaining three bits in the ID byte must be set to

110.

Figure 2. Address/Identification Byte Format

Instruction Byte

The next byte sent to the X9421 contains the

instruction and register pointer information. The four

most signiﬁcant bits are the instruction. The next two

bits point to one of four Data Registers. The format is

shown below in Figure 3.

Figure 3. Instruction Byte Format

0A0

Device Type

Identifier

Device Address

Select

Instructions

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCK

UP/DN

IF WCR = 00[H] THEN VW = VL

IF WCR = 3F[H] THEN VW = VH

Wiper

(WCR)

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