X1228 datasheet(13/31 Pages) XICOR

13 / 31 page

X1228

REV 1.3 3/24/04

Characteristics subject to change without notice.

13 of 31

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STATUS REGISTER (SR)

The Status Register is located in the CCR memory

map area at address 003Fh. This is a volatile register

only and is used to control the WEL and RWEL write

enable latches, read two power status and two alarm

bits. This register is separate from both the array and

the Clock/Control Registers (CCR).

Table 2. Status Register (SR)

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

from VBACK, not VCC. It is a read-only bit and is set/

reset by hardware (X1228 internally). Once the device

begins operating from VCC, the device sets this bit to

“0”.

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 0 or alarm 1 match

the real time clock. If there is a match, the respective

bit is set to ‘1’. The falling edge of the last data bit in a

SR Read operation resets the ﬂags. Note: Only the AL

bits that are set when an SR read starts will be reset.

An alarm bit that is set by an alarm occurring during an

SR read operation will remain set after the read opera-

tion is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior

to any writes to the Clock/Control Registers. Writes to

RWEL bit do not cause a nonvolatile write cycle, so the

device is ready for the next operation immediately after

the stop condition. A write to the CCR requires both

the RWEL and WEL bits to be set in a speciﬁc

sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and mem-

ory array during a write operation. This bit is a volatile

latch that powers up in the LOW (disabled) state. While

the WEL bit is LOW, writes to the CCR or any array

address will be ignored (no acknowledge will be issued

after the Data Byte). The WEL bit is set by writing a “1”

to the WEL bit and zeroes to the other bits of the Sta-

tus Register. Once set, WEL remains set until either

reset to 0 (by writing a “0” to the WEL bit and zeroes to

the other bits of the Status Register) or until the part

powers up again. Writes to WEL bit do not cause a

nonvolatile write cycle, so the device is ready for the

next operation immediately after the stop condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is a

read only bit that is set by hardware (X1228 internally)

when the device powers up after having lost all power

to the device. The bit is set regardless of whether VCC

or VBACK is applied ﬁrst. The loss of only one of the

supplies does not result in setting the RTCF bit. The

ﬁrst valid write to the RTC after a complete power fail-

ure (writing one byte is sufﬁcient) resets the RTCF bit

to ‘0’.

Unused Bits:

This device does not use bits 3 or 4 in the SR, but must

have a zero in these bit positions. The Data Byte out-

put during a SR read will contain zeros in these bit

locations.

CONTROL REGISTERS

The Control Bits and Registers, described under this

section, are nonvolatile.

Block Protect Bits—BP2, BP1, BP0

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write protected. A write to a

protected block of memory is ignored. The block protect

bits will prevent write operations to one of eight segments

of the array. The partitions are described in Table 3 .

Table 3. Block Protect Bits

Watchdog Timer Control Bits—WD1, WD0

The bits WD1 and WD0 control the period of the

Watchdog Timer. See Table 4 for options.

Addr

003Fh

BAT

AL1

AL0

RWEL

WEL

RTCF

Default

Protected Addresses

X1228

Array Lock

None

None (Default)

180h – 1FFh

Upper 1/4

100h – 1FFh

Upper 1/2

000h – 1FFh

Full Array

000h – 03Fh

First Page

000h – 07Fh

First 2 pgs

000h – 0FFh

First 4 pgs

000h – 1FFh

First 8 pgs

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