WM9713L datasheet(26/111 Pages) WOLFSON

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WM9713L

Preliminary Technical Data

PTD, March 2004, Rev 2.2

LEFT CHANNEL

RIGHT CHANNEL

PCMFS

PCMCLK

PCMADC /

PCMDAC

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 9 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of PCMCLK following a PCMFS

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of one

sample and the MSB of the next.

LEFT CHANNEL

RIGHT CHANNEL

PCMFS

PCMCLK

PCMADC/

PCMDAC

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 10 I

2S Justified Audio Interface (assuming n-bit word length)

CONTROL

The register bits controlling PCM audio format, word length and operating modes are summarised

below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE

must be set to specify master/slave modes.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CTRL

Sets function and control registers for GPIO /

PCM interface pins.

0 = GPIO pins as GPIOs

1 = GPIO pins configured as PCM interface

and controlled by this register

14:13

MODE

PCM interface mode when CTRL=1

00 = PCM interface disabled [PCMCLK tri-

stated, PCMFS tri-stated]

01 = PCM interface in slave mode [PCMCLK

as input, PCMFS as input]

10 = PCM interface in master mode [PCMCLK

as output, PCMFS as output]

11 = PCM interface in partial master mode

[PCMCLK as output, PCMFS as input]

36h

PCM

Control

SWAP

PCM data swap

0 = DAC data input on PCMDAC, ADC data

output on PCMADC

1 = DAC data input on PCMADC, ADC data

output on PCMDAC

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