WM8753 datasheet(46/87 Pages) WOLFSON

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Advanced Information

WM8753L

AI Rev 3.1 June 2004

Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor.

This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and

L/ROUT1, L/ROUT2 and MONO1 can be controlled using the VROI bit in register 27. The default is

low (500

Ω), so that any capacitors on the outputs can charge up quickly at start-up. If a high

impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to

about 90k

Ω.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R45 (2Dh)

Additional (1)

VROI

VREF to analogue output resistance

0: 500

Ω

1: 90 k

Ω

Table 43 Disabled Outputs to VREF Resistance

HEADPHONE SWITCH

Pin 43 (GPIO4) can be used as a headphone switch control input to automatically disable the speaker

output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this

mode, enabled by setting HPSWEN, pin 43 switches between headphone and speaker outputs (e.g.

when pin 43 is connected to a mechanical switch in the headphone socket to detect plug-in). The

HPSWPOL bit reverses the polarity of pin 43. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits

in register 22 must also be set for headphone and speaker output (see Table 44 and Table 45). The

GPIO4 pin has an internal pull-up/pull-down which can be enabled by setting register bits

GPIO4M[1:0]. For cap-less headphone connections a pull-down should be used if VMID is greater

than GPIO4 VIH, otherwise a pull-up should be used.

GPIO4 can also be used to generate an

interrupt. See GPIO and Interrupt Controller Section. The GPIO4 input has a debounce circuit to

remove glitches on the input caused by a jack insert in order to prevent the outputs being powered on

and off. This debounce circuit is clocked from a slow clock with period = 2

21 x input clock. The input

clock can be selected to be either mclk or pcmclk using SLWCLK.

HPSWEN

HPSWPOL

GPIO4

(pin 43)

L/ROUT1

(reg. 22)

L/ROUT2

(reg. 22)

Headphone

enabled

Speaker

enabled

yes

Table 44 Headphone Switch Operation

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

HPSWEN

Headphone Switch Enable

0 : Headphone switch disabled

1 : Headphone switch enabled

R45 (2Dh)

Output

Control

HPSWPOL

Headphone Switch Polarity

0 : GPIO4 high = headphone

1 : GPIO4 high = speaker

R52 (34h)

Clock Control

SLWCLK

Timeout and Headphone switch clock

source

0 = mclk

1 = pcm clk

Table 45 Headphone Switch

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