ADP7182ACPZ-5.0-R7 datasheet(29/31 Pages) AD

номер детали	ADP7182ACPZ-5.0-R7

подробное описание детали	Positive or negative enable logic

PDF	31 Pages

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производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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29 / 31 page

Data Sheet

ADP7182

Rev. I | Page 29 of 31

Table 11. Recommended LDOs for Very Low Noise Operation

Device

Number

VIN

Range (V)

VOUT

Fixed (V)

VOUT

Adjust

(V)

IOUT

(mA)

IQ at

IOUT

(µA)

IGND-SD

Max

(µA)

Soft

Start

PGOOD

Noise

(Fixed)

10 Hz to

100 kHz

(µV rms)

PSRR

100 kHz

(dB)

PSRR

1 MHz

(dB)

Package

ADP7102

3.3 to 20

1.5 to 9

1.22 to

300

750

Yes

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7104

3.3 to 20

1.5 to 9

1.22 to

500

900

Yes

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7105

3.3 to 20

1.8, 3.3, 5

1.22 to

500

900

Yes

3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7118

2.7 to 20

1.2 to 5

1.2 to 19

200

160

Yes

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142

2.7 to 40

1.2 to 5

1.2 to 39

200

160

Yes

2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7182

−2.7 to

−28

−1.8 to

−5

−1.22 to

−27

−200

−650

−8

2 mm × 2 mm

6-lead LFCSP,

3 mm × 3 mm

8-lead LFCSP,

5-lead TSOT

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