Rev 21 Jan 2014 15:09 | Page 21

R

SS12 Pin

SS34 Pin

(kΩ) (kΩ) CH1 CH2

CH3 CH4

0

N/A

2 ms 2 ms

2 ms 2 ms

100 600

2 ms Parallel 2 ms 4 ms

200 500

2 ms 8 ms

2 ms 8 ms

300 400

4 ms 2 ms

4 ms 2 ms

400 300

4 ms 4 ms

4 ms 4 ms

500 200

8 ms 2 ms

4 ms 8 ms

600 100

8 ms Parallel 8 ms 2 ms

N/A 0

8 ms 8 ms

8 ms 8 ms

Changing Channel 1/Channel 2 to a 2-Phase Parallel Output

Channel 1 and Channel 2 are programmed as individual outputs on the ADP5051/ADP5053 evaluation

boards. To configure Channel 1/Channel 2 as a 2-phase parallel output operation, the following steps

are required:

Short the jumper, S4.

1.

Change R39 = 100 kΩ and R16 = 600 kΩ (or R39 = 600 kΩ and R16 = 100 kΩ) in the SS12 pin

2.

setting.

Remove R17 and C8 from the COMP2 pin.

3.

Remove R4, and replace R29 with 0 Ω on the FB2 pin.

4.

Shunt the J-EN2 jumper to low.

5.

Use the FB1 pin (R2 and R28) to set the output voltage.

6.

Use J-EN1 (EN1 pin) to enable or disable the regulator.

7.

During the parallel configuration, the input voltage and the current-limit threshold for both channels

should be the same, and FPWM mode operation on both Channel 1 and Channel 2 are recommended.

See the ADP5051/ADP5053 data sheet for details regarding 2-phase parallel output.

Changing the Phase Shift (0°, 90°, 180°, 270°) in the Buck Regulators

On the ADP5051/ADP5053 evaluation board, the phase shift is 180° between Channel 1 and Channel

2, and 180° between Channel 3 and Channel 4. Channel 1 and Channel 3 operate in 0° phase shift.

With the ADP5050 only, the phase shift can be programmed at 0°, 90°, 180°, or 270° from Channel 2

to Channel 4 with reference to Channel 1 via PHASE2, PHASE3, and PHASE4 in the ADP5051 GUI

software. See the ADP5051/ADP5053 data sheet for details regarding 2-phase parallel output.

Changing the Power-Good (PWRGD) Output Options

On the ADP5051/ADP5053 evaluation board, the PWRGD output becomes active high when the

selective regulator is under normal operation. The PWRGD hardware output is logically AND'ed of an