8

 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1405B

While components connecting to C-Delay, OVP_S, EN,S-

MOD, DSPS_DR and PRDY are relatively non-critical, tight

placement and short,wide traces must be used in layout

of The Drives, DRN, and especially PGND pin. The top

gate driver supply voltage is provided by bootstrapping

the +5V supply and adding it the phase node voltage

(DRN). Since the bootstrap capacitor supplies the charge

to the TOP gate, it must be less than .5” away from the

SC1405. Ceramic X7R capacitors are a good choice for

supply bypassing near the chip. The Vcc pin capacitor

must also be less than .5” away from the SC1405. The

ground node of this capacitor, the SC1405 PGND pin

and the Source of the bottom FET must be very close to

each other, preferably with common PCB copper land

and multiple vias to the ground plane (if used). The par-

allel Shottkey must be physically next to the Bottom FETS

Drain and source. Any trace or lead inductance in these

connections will drive current way from the Shottkey and

allow it to flow through the FET’s Body diode, thus reduc-

ing efficiency.

Preventing Inadvertent Bottom FET Turn-on

At high input voltages, (12V and greater) a fast turn-on

of the top FET creates a positive going spike on the Bot-

tom FET’s gate through the Miller capacitance, Crss of

the bottom FET. The voltage appearing on the gate due

to this spike is:

Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous imped-

ance of the capacitors. (since dV/dT and thus the effec-

tive frequency is very high). If the BG pin of the SC1405B

is very close to the bottom FET, Vspike will be reduced

depending on trace inductance, rate if rise of current,etc.

While not shown in Figure 4, a capacitor may be added

from the gate of the Bottom FET to its source, preferably

less than .5” away. This capacitor will be added to Ciss

in the above equation to reduce the effective spike volt-

age, Vspike.

The selection of the bottom MOSFET must be done with

attention paid to the Crss/Ciss ratio. A low ratio reduces

the Miller feedback and thus reduces Vspike. Also

Applications Information

MOSFETs with higher Turn-on threshold voltages will con-

duct at a higher voltage and will not turn on during the

spike. The MOSFET shown in the schematic (figure 4)

has a 2 volt threshold and will require approximately 5

volts Vgs to be conducting, thus reducing the possibility

of shoot-through. A zero ohm bottom FET gate resistor

will obviously help keeping the gate voltage low.

Ultimately, slowing down the top FET by adding gate re-

sistance will reduce di/dt which will in turn make the ef-

fective impedance of the capacitors higher, thus allow-

ing the BG driver to hold the bottom gate voltage low.

Ringing on the Phase Node

The top MOSFET source must be close to the bottom

MOSFET drain to prevent ringing and the possibility of

the phase node going negative. This frequency is deter-

mined by:

Where:

L

to trace inductance of the connection between top FET’s

source and the bottom FET’s drain added to the trace

resistance of the bottom FET’s ground connection.

Coss=Drain to source capacitance of bottom FET. If there

is a Shottkey used, the capacitance of the Shottkey is

added to the value.

Although this ringing does not pose any power losses

due to a fairly high Q, it could cause the phase node to

go too far negative, thus causing improper operation,

double pulsing or at worst driver damage. This ringing is

also an EMI nuisance due to its high resonant frequency.

Adding a capacitor, typically 1000-2000pf, in parallel with

Coss can often eliminate the EMI issue. If double puls-

ing is caused due to excessive ringing, placing 4.7-10

ohm resistor between the phase node and the DRN pin

of the SC1405 should eliminate the double pulsing.

The negative voltage spikes on the phase node adds to

the bootstrap capacitor voltage, thus increasing the volt-

age between VBST - VDRN. If the phase node negative

spikes are too large, the voltage on the boost capacitor

could exceed device’s absolute maximum rating of 8V.

ISS

RSS

RSS

IN

SPIKE

C

C

(

C

*

V

V

+

=

OSS

ST

RING

C

*

L

(

*

2

(

1

F

Π

=