ADF4355-2

Data Sheet

Rev. B | Page 20 of 37

F24

F23

..........

F2

F1

MAIN FRACTIONAL VALUE (FRAC1)

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

16777212

1

1

..........

0

1

16777213

1

1

..........

1

0

16777214

1

1

.........

1

1

16777215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

F24

F23

F22

F21

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

CONTROL

BITS

F20

F19

F18

F17

F16

F15

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C3(0) C2(0) C1(1)

C4(0)

0

0

0

Figure 31. Register 1

REGISTER 1

Control Bits

With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 31

shows the input data format for programming this register.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0.

24-Bit Main Fractional Value

The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the

fraction that is input to the sigma-delta (Σ-Δ) modulator. This

fraction, along with the INT value, specifies the new frequency

channel that the synthesizer locks to, as shown in the RF

Synthesizer—A Worked Example section. FRAC1 values from 0

to (MOD1 − 1) cover channels over a frequency range equal to

the PFD reference frequency.