ADE9078 datasheet(50/108 Pages) AD

50 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 49 of 107

The ZX_SRC_SEL in the CONFIG0 register sets whether data

going into the zero-crossing detection circuit comes before or

after the high-pass filter, integrator, and phase compensation.

By default, the data after phase compensation is used. Note that

the high-pass filter has settling times given in Table 10. Thus, for

a fast response, it is recommended to set ZX_SRC_SEL to look for

a zero crossing before the high-pass filter. If the high-pass filter

is disabled with HPFDIS = 1 or if ZX_SRC_SEL = 1, note that a

dc offset on the input may cause the time between negative to

positive and positive to negative zero crossings and positive to

negative to negative to positive zero crossings to change,

indicating that the ZX detection does not have a 50% duty cycle.

The current and voltage signals are low-pass filtered to remove

harmonics. The low-pass filter, LPF1, has a corner of 85 Hz and

the equation is as follows:

( ) 1–

–

)

(

The low-pass filter settling time is 51 samples, 51/4 kSPS, which

results in 12.75 ms.

Figure 70 shows the delay between the detected zero-crossing

signal and the input. Note that there is a 4.3 ms delay between

the input signal zero crossing and the ZX zero crossing indication,

with a 50 Hz input signal. Zero crossings are generated on both

negative to positive and positive to negative transitions.

IA, IB, IC,

ORVA, VB, VC

4.3ms AT 50Hz

0.86

LPF1 OUTPUT

Figure 70. Zero Crossing Detection on Voltage and Current Channels

To provide protection from noise, voltage channel zero-crossing

events (ZXVA, ZXVB, and ZXVC) are not generated if the absolute

value of the LPF1 output voltage is smaller than the threshold,

ZXTHRSH. The current channel zero-crossing detection outputs

(ZXIA, ZXIB, and ZXIC) are active for all input signals levels.

Calculate the voltage channel zero-crossing threshold,

ZXTHRSH, from the following equation:

ZXTHRSH =

(

) (

)

Attenuatio

LPF1

Scale

Full

PCF

where:

V_PCF at Full Scale is ±74,680,000d.

LPF1 Attenuation is 0.86 at 50 Hz, and 0.81 at 60 Hz, the gain

attenuation of the LPF1 filter.

X is the dynamic range below which the voltage channel zero-

crossing must be blocked.

For example, assume that the full-scale input corresponds to

440 V rms. To prevent signals 100× lower than full scale (signals

smaller than 4.4 V rms) from generating a voltage channel zero-

crossing output, set ZXTHRSH to 78d.

(

) (

)

100

000

680

ZXTHRSH

Additionally, to prevent false zero crossings after a zero crossing

is generated, 1 ms must elapse before the next zero crossing can

be output.

Combined Voltage Zero Crossing

Phase A, Phase B, and Phase C voltage channel signals are

combined to generate one zero-crossing signal, ZX_COMB,

which is stable even if one or more phases drops out.

The input to the zero-crossing detection is (VA + VB − VC)/2

with the signal chain corresponding to Figure 71. As described

in the Applications Information section, the ADE9078 can meter

different polyphase configurations. The VCONSEL bits indicate

this selection. If VCONSEL is not equal to 0, the VB component

in the combined zero-crossing circuit is set to zero.

Use the same precautions to prevent noise from generating

zero-crossing interrupts on this output. As described in the

Zero-Crossing Detection section, signals below the ZXTHRSH

threshold do not generate ZXCOMB outputs, and a minimum

of 1 ms is required between ZXCOMB generations.

Zero-Crossing Output Rates

Seven zero-crossing detection circuits monitor the IA, IB, IC,

VA, VB, VC, and the combined (VA + VB − VC)/2 signals. The

zero-crossing detection circuits have two output rates: 4 kSPS

and 512 kSPS. The 4 kSPS zero-crossing signal is used to

calculate the line period, sent to the ZXx bits in the STATUS1

sequence error detection, resampling, and energy accumulation

functions. The 512 kSPS signal is used for angle measurements

and is output on the CF3/ZX pin if the CF3_CFG bit in the

CONFIG1 register = 1.

Table 21 indicates which zero-crossing edges (negative to

positive and positive to negative) are used for each function and

indicates what happens if a zero crossing is blocked because the

input signal is below the user configured ZXTHRSH.

The CF3/ZX output pin goes from low to high when a negative

to positive transition is detected and from high to low when a

positive to negative transition occurs. The ZX_SEL bits in the

ZX_LP_SEL register select the zero-crossing output used for

line cycle energy accumulation and the ZX output pin.

ADE9078 датащи(PDF) 50 Page - Analog Devices

ADE9078 датащи(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL