AD5675

Data Sheet

Rev. B | Page 8 of 26

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

A1

A0

SCL

RESET

RSTSEL

LDAC

SDA

GAIN

GND

TOP VIEW

(Not to Scale)

AD5675

Figure 4. TSSOP Pin Configuration

Table 7. TSSOP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.

2

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

3

parallel with a 0.1 µF capacitor to GND.

4

Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.

5

SCL

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift

register.

6

A0

Address Input. This pin sets the first LSB of the 7-bit slave address.

7

A1

Address Input. This pin sets the second LSB of the 7-bit slave address.

8

GAIN

9

Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

10

Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

11

Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

12

Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

13

GND

Ground Reference Point for All Circuitry on the Device.

14

RSTSEL

eight DACs to midscale.

15

LDAC

Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all

DAC registers to be updated if the input registers have new data, which allows all DAC outputs to simultaneously

update. This pin can also be tied permanently low.

16

SDA

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift

register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor.

17

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.

When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending

on the state of the RSTSEL pin.

18

Reference Input Voltage.

19

Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.

20

Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.