MB95F613K datasheet(23/110 Pages) CYPRESS

23 / 110 page

Document Number: 002-04698 Rev. *A

Page 23 of 110

PRELIMINARY

MB95610H Series

10. Block Diagram

Reset with LVD

Dual operation Flash with

security function

(36/20/12 Kbyte)

F2MC-8FX CPU

RAM (1024/512 bytes)

Oscillator

circuit

CR oscillator

Clock control

Interrupt controller

PLL

8/16-bit composite timer ch. 0

8/10-bit A/D converter

LCDC

(4 COM or 8 COM)

16-bit reload timer ch. 0

8/16-bit composite timer ch. 1

UART/SIO ch. 0

8/16-bit PPG ch. 0

8/16-bit PPG ch. 1

Port

PF2*1/RST*2

PF1/X1*2

PF0/X0*2

PG2/X1A*2

PG1/X0A*2

Watch counter

P14/UCK0

P13/UO0

P15/UI0

UART/SIO ch. 1

P22/UCK1

P21/UO1

P23/UI1

P24/PPG00

P25/PPG01

P06/PPG10

P07/PPG11

On-chip debug

Wild register

External interrupt

P00/INT00 to P03/INT03,

P30/INT04 to P33/INT07

P12*1/DBG

P52/TO00

P50/TO01

P51/EC0

P00/AN00 to P03/AN03

P05/ADTG

P90/V4 to P94/V0

COM0 to COM3

P04/SEG32 to P07/SEG35

P20/SEG44 to P27/SEG51

SEG00 to SEG31

P30/SEG36 to P37/SEG43

P90/V4 to P94/V0

4 COM mode:

8 COM mode:

COM0 to COM7

P04/SEG32 to P07/SEG35

P20/SEG44 to P27/SEG51

SEG04 to SEG31

P30/SEG36 to P37/SEG43

P34/TO11

P35/TO10

P36/EC1

I2C bus interface ch. 0

P27/SDA

P26/SCL

P20/TI0

P37/TO0

Vcc

Vss

*1:

*2:

*3:

P12 and PF2 are N-ch open drain pins.

Software select

When the event counter operating mode is enabled, 8/16-bit composite timer ch. 1 and the 16-bit reload timer ch. 0 can function as an event counter.

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