HMC7043LP7FE datasheet(13/44 Pages) AD

номер детали	HMC7043LP7FE

подробное описание детали	JEDEC JESD204B support

PDF	44 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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13 / 44 page

HMC7043

Data Sheet

Rev. B | Page 12 of 43

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

TIME (ns)

Figure 9. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL

–0.5

0.5

1.0

1.5

2.0

2.5

–0.6

–0.4

–0.2

0.2

0.4

0.6

200

400

600

800

1000

TIME (ns)

CLKOUT0

CLKOUT2

VALID PHASE ALARM

Figure 10. Output Channel Synchronization Before and After Rephase

–0.5

0.5

1.0

1.5

2.0

2.5

–0.6

–0.4

–0.2

0.2

0.4

0.6

330

335

340

345

350

TIME (ns)

CLKOUT0

CLKOUT2

VALID PHASE ALARM

Figure 11. Output Channel Synchronization Before Rephase

–0.6

–0.4

–0.2

0.2

0.4

0.6

695

700

705

710

715

TIME (ns)

CLKOUT0

CLKOUT2

VALID PHASE ALARM

–0.5

0.5

1.0

1.5

2.0

2.5

Figure 12. Output Channel Synchronization After Rephase

DELAY STEP

–40°C

+25°C

+85°C

Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,

LVPECL at 983.04 MHz

–200

–100

100

200

300

400

500

600

700

800

10 12 14 16 18 20 22 24 26 28 30

DELAY STEP

FUND:FUNDAMENTAL MODE AT 2949.12MHz

DIS: ANALOG DELAY IS DISABLED AT 983.04MHz

–40°C

+27°C

+85°C

Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at

983.04 MHz

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