For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

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HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Table 9. Reg 02h REFDIV Register

Bit

name

Width

Default

Description

[13:0]

rdiv

14

1

reference Divider ’r’ Value (EQ 4)

00h - illegal

01h - divide-by-1 (bypass)

10h - divide-by-2

11h - divide-by-3 etc

...

3FFFh - divide-by-16, 383

the reference divider is controlled by several bits in register 8. See register 8 description

for details.

Table 10. Reg 03h Frequency Register - Integer Part

Bit

name

Width

Default

Description

[15:0]

intg

16

c8h

Vco Divider integer part, used in all modes, see (EQ 4)

Fractional Mode

min 36d

max 2ˆ16 -1 = 65,535d

Integer Mode

min 32d

max 2ˆ16+31 = 65,567d

Table 11. Reg 04h Frequency - Fractional Part Register

Bit

name

Width

Default

Description

[23:0]

frac

24

0

Vco Divider Fractional part (24 bit unsigned) see section

Fractional Frequency tuning

Used in Fractional Mode only

min 0d

max 2^24-1

Table 12. Reg 05h SD Seed Register

Bit

name

Width

Default

Description

[23:0]

seed

24

0

Fractional Mode: Seeds fractional modulator

FSK Mode: Sets f1 in FSK mode when fsk_enable=1 (see section FSK Modulation)

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