their high ESR, as compared to ceramic capacitors. For

most applications, ceramic capacitors with X7R or X5R tem-

perature characteristic are preferred for use with the

LM3570. These capacitors have tight capacitance tolerance

85˚C). Capacitors with Y5V and/or Z5U temperature charac-

teristic are generally not recommended. These types of ca-

pacitors typically have wide capacitance tolerance (+80%,

-20%), vary significantly over temperature (Y5V: +22%,

-82% over -30˚C to +85˚C range; Z5U: +22%, -56% over

+10˚C to +85˚C range), and have poor voltage coefficients.

Under some conditions, a nominal 1µF Y5V or Z5U capacitor

could have a capacitance of only 0.1µF. Such detrimental

deviation is likely to cause these Y5V and Z5U of capacitors

to fail to meet the minimum capacitance requirements of the

LM3570.

POWER DISSIPATION

The maximum allowable power dissipation that this package

is capable of handling can be determined as follows:

P

θ

JA

Where T

ambient temperature, and

θ

JA

is the junction-to-ambient

thermal resistance of the specified package. The LM3570

comes in the LLP-14 package that has a junction-to-ambient

thermal resistance (

θ

θ

highly dependant upon the layout of the PC board (See the

PCB Layout Considerations section of this datasheet for

more information). The actual power dissipated by the

LM3570 follows the equation:

P

Where N equals the number of active outputs, V

LED forward voltage, I

by the Dx outputs, V

4.35V), and I

charge pump. Power dissipation must be less than that

allowed by the package. Please refer to the Absolute Maxi-

mum Rating of the LM3570.

THERMAL PROTECTION

The LM3570 has internal thermal protection circuitry to dis-

able the part if the junction temperature exceeds 150˚C. This

feature will protect the device from damage due to excessive

power dissipation. The device will recover and operate nor-

mally when the junction temperature falls below 140˚C. It is

important to have good thermal conduction with a proper

layout to reduce thermal resistance.

PCB LAYOUT CONSIDERATIONS

The LLP is a leadframe based Chip Scale Package (CSP)

with very good thermal properties. This package has an

exposed DAP (die attach pad) at the center of the package

measuring 3.0mm x 1.6mm. The main advantage of this

exposed DAP is to offer lower thermal resistance when it is

soldered to the thermal land on the PCB. For PCB layout,

National highly recommends a 1:1 ratio between the pack-

age and the PCB thermal land. To further enhance thermal

conductivity, the PCB thermal land may include vias to a

ground plane. For more detailed instructions on mounting

LLP packages, please refer to National Semiconductor Ap-

plication Note AN-1187.

www.national.com

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