LM628 datasheet(17/24 Pages) NSC

17 / 24 page

Data Reporting Commands (Continued)

Bit 3, the index-pulse acquired interrupt flag, is set to logic

one when an index pulse has occurred (if command SIP had

been executed) and indicates that the index position register

has been updated. The flag is functional independent of the

host interrupt mask status. Bit 3 is cleared by command

RSTI.

Bit 2, the trajectory complete interrupt flag, is set to logic one

when the trajectory programmed by the LTRJ command and

initiated by the STT command has been completed. Be-

cause of overshoot or a limiting condition (such as com-

manding the velocity to be higher than the motor can

achieve), the motor may not yet be at the final commanded

position. This bit is the logical OR of bits 7 and 10 of the Sig-

nals Register, see command RDSIGS below. The flag func-

tions independently of the host interrupt mask status. Bit 2 is

cleared via command RSTI.

Bit 1, the command-error interrupt flag, is set to logic one

when the user attempts to read data when a write was ap-

propriate (or vice versa). The flag is functional independent

of the host interrupt mask status. Bit 1 is cleared via com-

mand RSTI.

Bit 0, the busy flag, is frequently tested by the user (via the

host computer program) to determine the busy/ready status

prior to writing and reading any data. Such writes and reads

may be executed only when bit 0 is logic zero (not busy). Any

command or data writes when the busy bit is high will be ig-

nored. Any data reads when the busy bit is high will read the

current contents of the I/O port buffers, not the data ex-

pected by the host. Such reads or writes (with the busy bit

high) will not generate a command-error interrupt.

RDSIGS COMMAND: ReaD SIGnalS Register

Command Code:

0C Hex

Bytes Read:

Two

Data Range:

See Text

Executable During Motion: Yes

The LM628 internal “signals” register may be read using this

command. The first byte read is the more significant. The

less significant byte of this register (with the exception of bit

0) duplicates the status byte. See

Table 8.

TABLE 8. Signals Register Bit Allocation

Bit

Position

Function

Bit 15

Host Interrupt

Bit 14

Acceleration Loaded (But Not Updated)

Bit 13

UDF Executed (But Filter Not yet Updated)

Bit 12

Forward Direction

Bit 11

Velocity Mode

Bit 10

On Target

Bit 9

Turn Off upon Excessive Position Error

Bit 8

Eight-Bit Output Mode

Bit 7

Motor Off

Bit 6

Breakpoint Reached [Interrupt]

Bit 5

Excessive Position Error [Interrupt]

Bit 4

Wraparound Occurred [Interrupt]

Bit 3

Index Pulse Acquired [Interrupt]

Bit 2

Trajectory Complete [Interrupt]

Bit

Position

Function

Bit 1

Command Error [Interrupt]

Bit 0

Acquire Next Index (SIP Executed)

Bit 15, the host interrupt flag, is set to logic one when the

host interrupt output (Pin 17) is logic one. Pin 17 is set to

logic one when any of the six host interrupt conditions occur

(if the corresponding interrupt has not been masked). Bit 15

(and Pin 17) are cleared via command RSTI.

Bit 14, the acceleration-loaded flag, is set to logic one when

acceleration data is written to the LM628. Bit 14 is cleared by

the STT command.

Bit 13, the UDF-executed flag, is set to logic one when the

UDF command is executed. Because bit 13 is cleared at the

end of the sampling interval in which it has been set, this sig-

nal is very short-lived and probably not very profitable for

monitoring.

Bit 12, the forward direction flag, is meaningful only when the

LM628 is in velocity mode. The bit is set to logic one to indi-

cate that the desired direction of motion is “forward”; zero in-

dicates “reverse” direction. Bit 12 is set and cleared via com-

mand LTRJ. The actual setting and clearing of bit 12 does

not occur until command STT is executed.

Bit 11, the velocity mode flag, is set to logic one to indicate

that the user has selected (via command LTRJ) velocity

mode. Bit 11 is cleared when position mode is selected (via

command LTRJ). The actual setting and clearing of bit 11

does not occur until command STT is executed.

Bit 10, the on-target flag, is set to logic one when the trajec-

tory generator has completed its functions for the last-issued

STT command. Bit 10 is cleared by the next STT command.

Bit 9, the turn-off on-error flag, is set to logic one when com-

mand LPES is executed. Bit 9 is cleared by command LPEI.

Bit 8, the 8-bit output flag, is set to logic one when the LM628

is reset, or when command PORT8 is executed. Bit 8 is

cleared by command PORT12.

Bits 0 through 7 replicate the status byte (see ), with the ex-

ception of bit 0. Bit 0, the acquire next index flag, is set to

logic one when command SIP is executed; it then remains

set until the next index pulse occurs.

RDIP COMMAND: ReaD Index Position

Command Code:

09 Hex

Bytes Read:

Four

Data Range:

C0000000 to 3FFFFFFF Hex

Executable During Motion: Yes

This command reads the position recorded in the index reg-

ister. Reading the index register can be part of a system er-

ror checking scheme. Whenever the SIP command is ex-

ecuted, the new index position minus the old index position,

divided by the incremental encoder resolution (encoder lines

times four), should always be an integral number. The RDIP

command facilitates acquiring these data for host-based cal-

culations. The command can also be used to identify/verify

home or some other special position. The bytes are read in

most-to-least significant order.

RDDP COMMAND: ReaD Desired Position

Command Code:

08 Hex

Bytes Read:

Four

Data Range:

C0000000 to 3FFFFFFF Hex

Executable During Motion: Yes

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