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ICS950810

0472F—01/12/04

Assertion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

PCI_S TOP#

PCI_F[2:0] 33MHz

PCI[6:0] 33MHz

tsu

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch

low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next

rising edge.