916.50 MHz

Transceiver Module

RF Monolithics, Inc.

Phone: (972) 233-2903

Fax: (972) 387-8148

E-mail: info@rfm.com

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RFM Europe

Phone: 44 1963 251383

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http://www.rfm.com

©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.

DR3000-060404

Pin Descriptions

Pin

Name

Description

1

AGC/VCC

This pin is connected directly to the transceiver AGCCAP pin. To disable AGC operation, this pin is tied to VCC. To enable

AGC operation, a capacitor is placed between this pin and ground. This pin controls the AGC reset operation. A capacitor

between this pin and ground sets the minimum time the AGC will hold-in once it is engaged. The hold-in time is set to avoid

through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the

peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will

be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when

using OOK modulation with data pulses of at least 30 µs. Active or latched AGC operation is required for ASK modulation

and/or for data pulses of less than 30 µs. The AGC can be latched ON once engaged by connecting a 150 K resistor

between this pin and ground, instead of a capacitor. AGC operation depends on a functioning peak detector, as discussed

below. The AGC capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. Note that

provisions are made on the circuit board to install a jumper between this pin and the junction of C2 and L3. Installing the

jumper allows either this pin or Pin 7 to be used for the Vcc supply when AGC operation is not required.

2

PK DET

This pin is connected directly to the transceiver PKDET pin. This pin controls the peak detector operation. A capacitor

between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For most appli-

cations, the attack time constant should be set to 6.4 ms with a 0.027 µF capacitor to ground. (This matches the peak detec-

tor decay time constant to the time constant of the 0.1 µF coupling capacitor C3.) A ±10% ceramic capacitor should be used

at this pin. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC hold-

in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data

rates and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin

can be left unconnected, and the AGC pin can be connected to VCC to reduce the number of external components needed.

The peak detector capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. See the

description of Pin 3 below for further information.

3

RX BBO

This pin is connected directly to the transceiver BBOUT pin. On the circuit board, BBOUT also drives the transceiver CMPIN

process (DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal changes about 10 mV/dB, with a

peak-to-peak signal level of up to 675 mV. The signal at RX BBO is riding on a 1.1 Vdc value that varies somewhat with sup-

ply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to

500 K in parallel with no more than 10 pF is recommended. Note the AGC reset function is driven by the signal applied to

CMPIN through C3. When the transceiver is in power-down (sleep) or in a transmit mode, the output impedance of this pin

becomes very high, preserving the charge on the coupling capacitor(s). The value of C3 on the circuit board has been cho-

sen to match typical data encoding schemes at 2.4 kbps. If C3 is modified to support higher data rates and/or different data

encoding schemes and PK DET is being used, make the value of the peak detector capacitor about 1/3 the value of C3.

4

RX DATA

RX DATA is connected directly to the transceiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K parallel load.

The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down

(sleep) or transmit modes, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used

to establish a definite logic state when this pin is high impedance (do not connect the pull-up resistor to a supply voltage

higher than 3.5 Vdc or the transceiver will be damaged). This pin must be buffered to successfully drive low-impedance

loads.

5

TX IN

The TX IN pin is connected to the transceiver TXMOD pin through a 4.7 K resistor on the circuit board. Additional series

resistance will often be required between the modulation source and the TX IN pin, depending on the desired output power

and peak modulation voltage (3.3 K typical for a peak modulation voltage of 3 volts). Saturated output power requires about

450 µA of drive current. Peak output power PO for a 3 Vdc supply is approximately:

This pin must be held low in the receive and sleep modes. Please refer to section 2.9 of the ASH Transceiver Designer’s

Guide for additional information.

6

GND

This is a ground pin.