Philips Semiconductors

Product specification

PLUS405-37/-45

Programmable logic sequencers

(16

× 64 × 8)

1996 Nov 12

13

TIMING DEFINITIONS

SYMBOL

PARAMETER

Width of input clock pulse.

Minimum guaranteed clock period.

Required delay between beginning of valid input and positive transition of Clock.

Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low).

Required delay between beginning of valid Input and positive transition of Clock, when using optional Complement Array (two

passes necessary through the AND Array).

Required delay between positive transition of clock, and return of input I10, I11 or I12 from Diagnostic Mode (10V).

Minimum guaranteed operating frequency; input to output (CLK1 and CLK2).

Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2).

Minimum guaranteed internal operating frequency; with internal feedback from state register to state register.

Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through

Complement Array, to state register.

Minimum guaranteed clock frequency (register toggle frequency).

Interval between clock pulses.

Required delay between positive transition of Clock and end of valid Input data.

Delay between beginning of Output Enable Low and when Outputs become valid.

Delay between input I12 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register.

Required delay between inputs I11, I10 or I12 transition to Diagnostic Mode (10V), and when the output pins become available

as inputs.

Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to

guarantee that the clock edge is not detected as a valid negative transition.

Width of initialization input pulse.

Delay between beginning of Output Enable High and when Outputs are in the OFF–state.

Delay between positive transition of Initialization and when Outputs become valid.

Delay between input I12 transition to Logic mode and when the Outputs reflect the contents of the Output Register.

Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output

Registers in diagnostic mode.

Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding first

reliable clock pulse.