Preliminary

Avance Logic, Inc.

ALC202

- 13 -

Rev0.62

http://www.realtek.com.tw

11: S/PDIF source data assigned to AC-LINK slot10/11.

3

Reserved

2

R/W SPDIF 1: enable 0: disable (SPDIFO is in high impedance)

1

R/W DRA 1: enable 0: disable

0

R/W VRA. 1: enable 0: disable¶

Ê

If VRA = 0, ALC202 ADC/DAC operate at fixed 48KHz sampling rate. Otherwise, it

operates with variable sampling rate defined in MX2C and MX32. VRA also control write

operation of MX2Cand MX32.

MX2C

PCM DAC Rate

Default: BB80H

Bit

Type

Function

15:0

R/W FOSR[15:0]Output sampling rate.

Ê

ALC202 support the following sampling rate required in PC99/PC2001 design guide.

Sampling rate

FOSR[15:0]

8000

1F40h

11025

2B11h

12000

2EE0

16000

3E80h

22050

5622h

24000

5DC0

32000

7D00h

44100

AC44h

48000

BB80h

Note that If the value written is not support, the closest value is returned .

Ë

When MX2A.0=0 (VRA is disable), this register will return BB80h when read.

MX32

PCM ADC Rate

Default: BB80H

Bit

Type

Function

15:0

R/W FISR[15:0]Output sampling rate.

Ê

ALC202 support the following sampling rate required in PC99/PC2001 design guide.

Sampling rate

FISR[15:0]

8000

1F40h

11025

2B11h

12000

2EE0

16000

3E80h

22050

5622h

24000

5DC0

32000

7D00h

44100

AC44h

48000

BB80h

Note that If the value written is not support, the closest value is returned .

Ë

When MX2A.0=0 (VRA is disable), this register will return BB80h when read.

MX3A

S/PDIF Channel Status and Control

Default: 2000H

Bit

Type

Function

15

R/W Validity Control (control V bit in Sub-Frame)

0: the V bit (valid flag) in sub-frame depends on whether the S/PDIF data is

under-run or over-run.

1: the V bit in sub-frame is always send as 1 to indicate the invalid data is not

suitable for receiver.