Integrated Circuits Inc.

aP89021/010

Ver 4.0

Aug 23, 2010

14

℃

℃

℃, VDD = 3.3V, VSS = 0V, 8KHz sampling )

Symbol

Parameter

Min.

Typ.

Max.

Unit

Note

tKD

Key trigger debounce time

16





ms

1

tKD

Key trigger debounce time – retrigger

24





ms

1

tUP

Ramp up time

0

128/Fs

−−

s

3

tDN

Ramp down time

0

−−

256/Fs

s

3

tKDD

Key trigger delay after ramp down

−−

0

−−

ms

tSTPD

STOP pulse output delay time





256

µ

s

tSTPW

STOP pulse width



64



ms

1

tBD

BUSY signal output delay time





100

ns

tBH

BUSY signal output hold time



100



ns

tASH

Address set-up /hold time

100





ns

tSBTW

SBT stroke pulse width

16





ms

1

tLEDC

LED flash frequency



3



Hz

2

Notes : 1. This parameter is inversely proportional to the sampling frequency.

2. This parameter is proportional to the sampling frequency.

3. Fs is sampling frequency in Hz

S1~S4,

SBT

COUT

STOP

BUSY

CPU Parallel Mode

SBT

Addr.

S1~S4

KEY Trigger Mode