 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
HCPL3180 датащи(PDF) 17 Page - Agilent(Hewlett-Packard) |
|
|
|||||||||||||||||||||||||||||
HCPL3180 датащи(HTML) 17 Page - Agilent(Hewlett-Packard) |
|
|
17 / 19 page  17 CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by over-driving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 8 mA to achieve 10 kV/us CMR. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit, which like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. Under Voltage Lockout Feature The HCPL-3180 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3180 supply voltage (equivalent to the fully charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3180 output is in the high state and the supply voltage drops below the HCPL- 3180 UVLO- threshold (typ 7.5 V) the optocoupler output will go into the low state. When the HCPL-3180 output is in the low state and the supply voltage rises above the HCPL-3180 VUVLO+ threshold (typ 8.5 V) the optocoupler output will go into the high state (assume LED is “ON”). Figure 34. Under Voltage Lock Out Figure 35. Minimum LED Skew for Zero Dead Time IPM Dead Time and Propagation Delay Specifications The HCPL-3180 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power invertor designs. Dead time is the time during which the high and low side power transistors are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails. 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 (VCC-VEE) - SUPPLY VOLTAGE - V |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
