BQ3285LF datasheet(2/22 Pages) TI

2 / 22 page

Block Diagram

Pin Descriptions

MOT

Bus type select input

MOT selects bus timing for either Motorola

or Intel architecture.

This pin should be

tied to VCC for Motorola timing or to VSS for

Intel timing (see Table 1).

The setting

should not be changed during system opera-

tion. MOT is internally pulled low by a 30K

Ω resistor.

AD0–AD7

Multiplexed address/data

input/output

The bq3285LF bus cycle consists of two

phases: the address phase and the

data-transfer phase.

The address phase

precedes the data-transfer phase.

During

the address phase, an address placed on

AD0–AD7 is latched into the bq3285LF on

the falling edge of the AS signal. During

the data-transfer phase of the bus cycle, the

AD0–AD7 pins serve as a bidirectional data

bus.

Address strobe input

AS serves to demultiplex the address/data

bus. The falling edge of AS latches the ad-

dress on AD0–AD7. This demultiplexing pro-

cess is independent of the CS signal. For

DIP and SOIC packages with MOT = VSS,

the AS input is provided a signal similar to

ALE in an Intel-based system.

Bus

Type

MOT

Level

Equivalent

R/W

Equivalent

Motorola

VCC

DS,E,or

Φ2

R/W

Intel

VSS

RD,

MEMR,or

I/OR

WR,

MEMW,or

I/OW

ALE

Table 1. Bus Setup

BD3285ID.eps

Bus

I/F

Power-

Fail

Control

Storage Registers

(114 Bytes)

User Buffer

(14 Bytes)

VOUT

Clock/Calendar, Alarm

and Control Bytes

Time-

Base

Oscillator

Control/Status

Registers

÷ 8

÷ 64

16 1 MUX

Interupt

Generator

Control/Calendar

Update

VCC

AD0–AD7

MOT

32K

INT

RST

R/W

Storage Registers

(126 Bytes)

Index Registers

(2 Bytes)

RCL

EXTRAM

Write

Protect

32K

Driver

MUX

bq3285LF

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