ADGS1412BCPZ datasheet(20/26 Pages) AD

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Data Sheet

ADGS1412

Rev. 0 | Page 19 of 25

SCLK Count Error Detection

SCLK count error detection allows the user to detect if an

incorrect number of SCLK cycles are sent by the microcontroller/

CPU. When in address mode, with CRC disabled, 16 SCLK

cycles are expected. If 16 SCLK cycles are not detected, the

SCLK count error flag asserts in the error flags register. When

less than 16 SCLK cycles are received by the device, a write to

the register map never occurs. When the ADGS1412 receives

more than 16 SCLK cycles, a write to the memory map still

occurs at the 16th SCLK rising edge, and the flag asserts in the

error flags register. With CRC enabled, the expected number of

SCLK cycles becomes 24. SCLK count error detection is enabled

by default and can be configured by the user through the error

configuration register.

Invalid Read/Write Address Error

An invalid read/write address error detects when a nonexistent

error asserts when a write to a read only register is attempted.

The invalid read/write address error flag asserts in the error

flags register when an invalid read/write address error happens.

The invalid read/write address error is detected on the nineth

SCLK rising edge, which means a write to the register never

occurs when an invalid address is targeted. Invalid read/write

address error detection is enabled by default and can be

disabled by the user through the error configuration register.

CLEARING THE ERROR FLAGS REGISTER

To clear the error flags register, write the special 16-bit SPI

frame, 0x6CA9, to the device. This SPI command does not

trigger the invalid R/W address error. When CRC is enabled,

the user must also send the correct CRC byte for a successful

error clear command. At the 16th or 24th SCLK rising edge, the

error flags register resets to zero.

BURST MODE

The SPI interface can accept consecutive SPI commands

without the need to de-assert the CS line, which is called burst

mode. Burst mode is enabled through the burst enable register.

This mode uses the same 16-bit command to communicate

with the device. In addition, the response of the device at SDO

is still aligned with the corresponding SPI command. Figure 38

shows an example of SDI and SDO during burst mode.

The invalid read/write address and CRC error checking functions

operate similarly during burst mode as they do during address

mode. However, SCLK count error detection operates in a

slightly different manner. The total number of SCLK cycles

within a given CS frame are counted, and if the total is not a

multiple of 16, or a multiple of 24 when CRC is enabled, the

SCLK count error flag asserts.

SDO

COMMAND0[15:0]

RESPONSE0[15:0]

COMMAND1[15:0]

RESPONSE1[15:0]

COMMAND2[15:0]

RESPONSE2[15:0]

COMMAND3[15:0]

RESPONSE3[15:0]

SDI

Figure 38. Burst Mode Frame

SOFTWARE RESET

When in address mode, the user can initiate a software reset.

To do so, write two consecutive SPI commands, namely 0xA3

followed by 0x05, targeting Register 0x0B. After a software

reset, all register values are set to default.

DAISY-CHAIN MODE

The connection of several ADGS1412 devices in a daisy-chain

configuration is possible, and Figure 39 illustrates this setup. All

devices share the same CS and SCLK line, whereas the SDO of a

device forms a connection to the SDI of the next device, creating a

shift register. In daisy-chain mode, SDO is an eight-cycle

delayed version of SDI. When in daisy-chain mode, all

commands target the switch data register. Therefore, it is not

possible to make configuration changes while in daisy-chain mode.

SDI

SCLK

SDO

ADGS1412

DEVICE 1

SDO

ADGS1412

DEVICE 2

SPI

INTERFACE

SPI

INTERFACE

Figure 39. Two ADGS1412 Devices Connected in a Daisy-Chain Configuration

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