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ADGS1412

Data Sheet

Rev. 0 | Page 18 of 25

THEORY OF OPERATION

The ADGS1412 is a set of serially controlled, quad SPST switches

with error detection features. SPI Mode 0 or SPI Mode 3 can be

used with the device, and it operates with SCLK frequencies up

to 50 MHz The default mode for the ADGS1412 is address mode

in which the registers of the device are accessed by a 16-bit SPI

command that is bounded by CS. The SPI command becomes

24 bit if the user enables CRC error detection. Other error detection

features include SCLK count error and invalid read/write error.

If any of these SPI interface errors occur, they are detectable by

reading the error flags register. The ADGS1412 can also operate

in two other modes, namely burst mode and daisy-chain mode.

The interface pins of the ADGS1412 are CS, SCLK, SDI, and SDO.

Hold CS low when using the SPI interface. Data is captured on

the SDI on the rising edge of SCLK, and data is propagated out on

the SDO on the falling edge of SCLK. SDO has an open-drain

output; thus, connect a pull-up to this output. When not pulled

low by the ADGS1412, SDO is in a high impedance state.

ADDRESS MODE

Address mode is the default mode for the ADGS1412 upon

power up. A single SPI frame in address mode is bounded by

a CS falling edge and the succeeding CS rising edge. It is comprised

of 16 SCLK cycles. The timing diagram for address mode is shown

in Figure 36. The first SDI bit indicates if the SPI command is a

read or write command. When the first bit is set to 0, a write

command is issued, and if the first bit is set to 1, a read command

is issued. The next seven bits determine the target register address.

The remaining eight bits provide the data to the addressed register.

The last eight bits are ignored during a read command, because

during these clock cycles SDO propagates out the data contained

in the addressed register.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the 9th to the 16th SCLK falling edge during SPI

reads. A register write occurs on the 16th SCLK rising edge

during SPI writes.

During any SPI command, SDO sends out eight alignment bits

on the first eight SCLK falling edges. The alignment bits observed

at SDO are 0x25.

ERROR DETECTION FEATURES

Protocol and communication errors on the SPI interface are

detectable. There are three detectable errors, which are incorrect

SCLK error detection, invalid read and write address error

detection, and CRC error detection. Each of these errors has a

corresponding enable bit in the error configuration register. In

addition, there is an error flag bit for each of these errors in the

error flags register.

Cyclic Redundancy Check (CRC) Error Detection

The CRC error detection feature extends a valid SPI frame by

8 SCLK cycles. These eight extra cycles are needed to send the CRC

byte for that SPI frame. The CRC byte is calculated by the SPI block

using the 16-bit payload: the R/W bit, Register Address Bits[6:0],

and Register Data Bits[7:0]. The CRC polynomial used in the

SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing

diagram with CRC enabled, see Figure 37. Register writes occur

at the 24th SCLK rising edge with CRC Error Checking enabled.

During a SPI write, the microcontroller/CPU provides the CRC

byte through SDI. The SPI block checks the CRC byte just before

the 24th SCLK rising edge. On this same edge, the register write

is prevented if an incorrect CRC byte is received by the SPI

interface. The CRC error flag is asserted in the error flags

During a SPI read, the CRC byte is provided to the microcontroller

through SDO.

The CRC error detection feature is disabled by default and can

be configured by the user through the error configuration register.

SDO

R/W

10111213141516

SDI

SCLK

Figure 36. Address Mode Timing Diagram

SDO

R/W

SDI

SCLK

Figure 37. Timing Diagram with CRC Enabled

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