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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8756 датащи(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8756 датащи(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 39 page  WM8756 Advance Information AI Rev 1.3 October 2001 8 MASTER CLOCK TIMING SCKI t SCKIL t SCKIH t SCKIY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information SCKI System clock pulse width high tSCKIH 13 ns SCKI System clock pulse width low tSCKIL 13 ns SCKI System clock cycle time tSCKIY 26 ns SCKI Duty cycle 40:60 60:40 Table 6 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE TIMING BCKIN DIN0/1/2 LRCIN t BCH t BCL t BL t LB t BCY t DS t DH Figure 2 PCM Digital Audio Data Timing Test Conditions AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLB 8ns LRCIN hold time from BCKIN rising edge tBL 8ns DIN0/1/2 set-up time to BCKIN rising edge tDS 8ns DIN0/1/2 hold time from BCKIN rising edge tDH 8ns Table 7 PCM Digital Audio Timing |
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