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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM505 датащи(PDF) 13 Page - Texas Instruments |
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DM505 датащи(HTML) 13 Page - Texas Instruments |
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13 / 286 page  Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 13 DM505 www.ti.com SPRS976A – NOVEMBER 2016 – REVISED JANUARY 2017 Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] AA6 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA8 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y8 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA7 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AB4 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y5 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA4 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y6 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA18 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y21 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA21 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y22 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA19 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB20 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy Y17 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AB18 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5/1.8 vdds_ddr3 NA LVCMOS DDR PUx/PDy AA3 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy AA2 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y3 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy V2 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy U3 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy V3 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy Y2 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 NA LVCMOS DDR PUx/PDy |
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