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WM8944BECS/R датащи(PDF) 95 Page - Cirrus Logic

номер детали WM8944BECS/R
подробное описание детали  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8944BECS/R датащи(HTML) 95 Page - Cirrus Logic

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WM8944B
Rev 4.3
95
R/W
A14
A13
A12
A2
A1
SDA
SCLK
CS
15-bit control register address
16-bit control register data
A0
B15
B14
B13
B2
B0
B1
Figure 41 3-Wire Serial Control Interface
POWER MANAGEMENT
The WM8944B has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it
is important to enable or disable these functions in the correct order, and to use the signal mute
registers as part of a carefully structured control sequence.
The power management control registers are described in Table 67.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
management
1
12
INPGA_ENA
0
Input PGA Enable
0 = Disabled
1 = Enabled
11
ADCR_ENA
0
Right ADC Enable
0 = Disabled
1 = Enabled
ADCR_ENA must be set to 1 when
processing right channel data from
the Digital Microphone.
10
ADCL_ENA
0
Left ADC Enable
0 = Disabled
1 = Enabled
ADCL_ENA must be set to 1 when
processing data from the ADC or
from the Left Digital Microphone.
4
MICB_ENA
0
Microphone Bias Enable
0 = Disabled
1 = Enabled
3
BIAS_ENA
0
Master Bias Enable
0 = Disabled
1 = Enabled
R3 (03h)
Power
management
2
14
OUT_ENA
0
LINEOUT enable
0 = Disabled
1 = Enabled
12
SPK_PGA_ENA
0
Speaker PGA enable
0 = Disabled
1 = Enabled



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