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WM8281ECS/R датащи(PDF) 37 Page - Cirrus Logic

номер детали WM8281ECS/R
подробное описание детали  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R датащи(HTML) 37 Page - Cirrus Logic

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WM8281
Rev 4.0
37
DIGITAL AUDIO INTERFACE - TDM MODE
When TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt
to drive the AIFnTXDAT pin simultaneously. To support this requirement, the AIFnTXDAT pins can be
configured to be tri-stated when not outputting data.
The timing of the AIFnTXDAT tri-stating at the start and end of the data transmission is described in
Figure 7 below.
BCLK
TXDAT
AIFnTXDAT enable time
AIFnTXDAT disable time
AIFnTXDAT undriven (tri-state)
AIFnTXDAT valid (CODEC output)
AIFnTXDAT valid
AIFnTXDAT undriven (tri-state)
Figure 7 Audio Interface Timing - TDM Mode
Test Conditions
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
TDM Timing - Master Mode
CLOAD (AIFnTXDAT) = 15pF to 25pF. BCLK slew (10% to 90%) = 3.7ns to 5.6ns.
AIFnTXDAT enable time from BCLK falling edge
0
ns
AIFnTXDAT disable time from BCLK falling edge
6
ns
TDM Timing - Slave Mode
CLOAD (AIFnTXDAT) = 15pF). BCLK slew (10% to 90%) = 3ns.
AIFnTXDAT enable time from BCLK falling edge
2
ns
AIFnTXDAT disable time from BCLK falling edge
10.7
ns
TDM Timing - Slave Mode
CLOAD (AIFnTXDAT) = 25pF). BCLK slew (10% to 90%) = 6ns
AIFnTXDAT enable time from BCLK falling edge
2
ns
AIFnTXDAT disable time from BCLK falling edge
12.7
ns



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