CS2000-CP datasheet(8/37 Pages) CIRRUS

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CS2000-CP

DS761F3

AC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);

TA = -40°C to +85°C (Automotive-D Grade); TA = -40°C to +105°C (Automotive-E Grade); CL =15pF.

Notes: 4. 1 UI (unit interval) corresponds to tSYS_CLK or 1/fSYS_CLK.

5. tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that

PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-

cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will

result in larger values of tCS.

6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information.

7. fCLK_OUT is ratio-limited when fCLK_IN is below 72 Hz.

8. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] =11.

9. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd

order 100 Hz to 40 kHz bandpass filter.

10. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd

order 100 Hz Highpass filter.

11. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.

12. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the

reference clock.

Parameters

Symbol

Conditions

Min

Typ

Max

Units

Crystal Frequency

Fundamental Mode XTAL

fXTAL

RefClkDiv[1:0] = 10

RefClkDiv[1:0] = 01

RefClkDiv[1:0] = 00

MHz

Reference Clock Input Frequency

fREF_CLK

RefClkDiv[1:0] = 10

RefClkDiv[1:0] = 01

RefClkDiv[1:0] = 00

MHz

Reference Clock Input Duty Cycle

DREF_CLK

Internal System Clock Frequency

fSYS_CLK

814

MHz

Clock Input Frequency

fCLK_IN

50 Hz

MHz

Clock Input Pulse Width (Note 4)pwCLK_IN

fCLK_IN < fSYS_CLK/96

fCLK_IN > fSYS_CLK/96

Clock Skipping Timeout

tCS

(Notes 5, 6)20

Clock Skipping Input Frequency

fCLK_SKIP

(Note 6)

50 Hz

kHz

PLL Clock Output Frequency

fCLK_OUT

(Note 7)6

MHz

PLL Clock Output Duty Cycle

tOD

Measured at VD/2

Clock Output Rise Time

tOR

20% to 80% of VD

1.7

3.0

Clock Output Fall Time

tOF

80% to 20% of VD

1.7

3.0

Period Jitter

tJIT

(Note 8)

ps rms

Base Band Jitter (100 Hz to 40 kHz)

(Notes 8, 9)

ps rms

Wide Band JItter (100 Hz Corner)

(Notes 8, 10)

175

ps rms

PLL Lock Time - CLK_IN (Note 11)tLC

fCLK_IN < 200 kHz

fCLK_IN > 200 kHz

100

200

PLL Lock Time - REF_CLK

tLR

fREF_CLK = 8 to 75 MHz

Output Frequency Synthesis Resolution (Note 12)ferr

High Resolution

High Multiplication

±0.5

±112

ppm

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