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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RTC4553 датащи(PDF) 2 Page - List of Unclassifed Manufacturers |
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RTC4553 датащи(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 2 page  48 Real time clock module Switching characteristics Block diagram Register table Timing chart 32.768 kHz TPOUT SOUT SCK SIN CS1 CS0 WR (Ta=-30˚C to +70˚C, VDD=5V ±10%, GND=OV) Note: ∗ TEST bit should be “0”. CS0 SCK SIN WR SOUT SOUT CS1 TPOUT SCK CS0 t WCKL t SD t SWR t DSZ1 t DSO t DPZ1 t DPZ2 t DSZ2 t PS t HWR t HD t WCKH t HCS 1/f CLK 10% 90% 90% 90% 10% 10% 90% 90% 90% 90% 10% 10% 10% 10% 90% 10% 10% tSCS SCK OSC Counter Output control RAM (120bit) Input control Output control Shift register Control circuit Control register 1 Control register 2 Control register 3 Sec. Min. Hou. Day of Week Day Mon. Year Address 0 1 2 3 4 5 6 7 8 9 A B C D E F A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE 0 Counter control register Register symbol S1 S10 MI1 MI10 H1 H10 W D1 D10 MO1 MO10 Y1 Y10 C1 C2 C3 D3 S8 0 mi8 0 h8 PM/AM 0 d8 0 mo8 0 y8 y80 TPS BUSY SYSR D2 S4 S40 mi4 mi40 h4 0 w4 d4 0 mo4 0 y4 y40 30ADJ PONC TEST D1 S2 S20 mi2 mi20 h2 h20 w2 d2 d20 mo2 0 y2 y20 CNTR — MS1 D0 S1 S10 mi1 mi10 h1 h10 w1 d1 d10 mo1 mo10 y1 y10 24/12 ∗ MS0 Register name 1-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register 10-hour digit register Day of the week digit register 1-day digit register 10-day digit register 1-month digit register 10-month digit register 1-year digit register 10-year digit register Control register 1 Control register 2 Control register 3 MODE 1 User RAM Domain 1 D3 RA3 RA7 RA11 RA15 RA19 RA23 RA27 RA31 RA35 RA39 RA43 RA47 RA51 RA55 RA59 D2 RA2 RA6 RA10 RA14 RA18 RA22 RA26 RA30 RA34 RA38 RA42 RA46 RA50 RA54 RA58 D1 RA1 RA5 RA9 RA13 RA17 RA21 RA25 RA29 RA33 RA37 RA41 RA45 RA49 RA53 RA57 D0 RA0 RA4 RA8 RA12 RA16 RA20 RA24 RA28 RA32 RA36 RA40 RA44 RA48 RA52 RA56 MODE 2 User RAM Domain 2 D3 RA63 RA67 RA71 RA75 RA79 RA83 RA87 RA91 RA95 RA99 RA103 RA107 RA111 RA115 RA119 D2 RA62 RA66 RA70 RA74 RA78 RA82 RA86 RA90 RA94 RA98 RA102 RA106 RA110 RA114 RA118 D1 RA61 RA65 RA69 RA73 RA77 RA81 RA85 RA89 RA93 RA97 RA101 RA105 RA109 RA113 RA117 D0 RA60 RA64 RA68 RA72 RA76 RA80 RA84 RA88 RA92 RA96 RA100 RA104 RA108 RA112 RA116 Same as MODE 0 Same as MODE 0 Item SCK ___ input frequency SCK ___ “L” time SCK ___ “H” time SCK ___ pause time CS0 __ setup time CS0 __ hold time SIN data setup time SIN data Hold time WR ___ setup time WR ___ hold time SOUT delay time CS0 __ , and CS1 enable to SOUT output CS0 __ disenable to SOUT high Z CS1 enable to SOUT output CS1 enable to SOUT high Z Symbol fSCK tWSCKL tWSCKH tPS tSCS tHCS tSD tHD tSWR tHWR tDSO tDSZ1 tDSZ2 tDPZ1 tDPZ2 Condition — — CL=100pF Min. — 1.0 0 0.5 0.2 1.0 0.5 — Typ. — — 150 — Max. 500 — — 500 100 Unit kHz µs ns |
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