Low-Power, 16-Bit Analog-to-Digital Converter

with Parallel Interface

8

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Detailed Description

Converter Operation

The MAX1165/MAX1166 use a successive-approxima-

tion (SAR) conversion technique with an inherent track-

and-hold (T/H) stage to convert an analog input into a

16-bit digital output. Parallel outputs provide a high-

speed interface to most microprocessors (µPs). The

Functional Diagram shows a simplified internal archi-

tecture of the MAX1165/MAX1166. Figure 3 shows a

typical application circuit for the MAX1166.

Analog Input

The equivalent input circuit is shown in Figure 4. A

switched capacitor digital-to-analog converter (DAC)

provides an inherent T/H function. The single-ended

input is connected between AIN and AGND.

Input Bandwidth

The ADC’s input-tracking circuitry has a 4MHz small-

signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid aliasing of

unwanted high-frequency signals into the frequency

band of interest, use anti-alias filtering.

Analog Input Protection

Internal protection diodes, which clamp the analog

the device.

If the analog input exceeds 300mV beyond the sup-

plies, limit the input current to 10mA.

D0–D15

D0–D15

1mA

DGND

DGND

1mA

Figure 1. Load Circuits

CS

R/C

REF POWER-

DOWN BIT

EOC

D0–D15

HBEN*

DATA VALID

D8/D15–

D0/D7*

HIGH-/LOW-

BYTE VALID

HIGH-/LOW-

BYTE VALID

*HBEN AND BYTE-WIDE DATA BUS

AVAILABLE ON MAX1166 ONLY.

HIGH-Z

HIGH-Z

Figure 2. MAX1165/MAX1166 Timing Diagram