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HT46R23 датащи(PDF) 16 Page - Holtek Semiconductor Inc

номер детали HT46R23
подробное описание детали  8-Bit OTP Microcontroller
PDF  42 Pages
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производитель  HOLTEK [Holtek Semiconductor Inc]
домашняя страница  http://www.holtek.com
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HT46R23
Rev. 1.30
16
August 17, 2001
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1. If the PWM function is
enabled, the PWM0/PWM1 signal will appear on
PD0/PD1 (if PD0/PD1 is operating in output mode). The
I/O functions of PD0/PD1 are as shown.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
PD1
Logical
Input
Logical
Output
Logical
Input
PWM0
PWM1
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
PWM
The microcontroller provides 2 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1. The PWM channels have their data registers
denoted as PWM0 (1AH) and PWM1 (1BH). The fre-
quency source of the PWM counter comes from fSYS.
The PWM registers are two 8-bit registers. The wave-
forms of PWM outputs are as shown. Once the
PD0/PD1 are selected as the PWM outputs and the out-
put function of PD0/PD1 are enabled (PDC.0/PDC.1
=²0²), writing 1 to PD0/PD1 data register will enable the
PWM output function and writing ²0² will force the
PD0/PD1 to stay at ²0².
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
Modulation cycle i
(i=0~3)
i<AC
DC 1
64
+
i³AC
DC
64
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
V DD
M
U
X
M
U
X
PF D E N
(P A 3 )
OP 0 ~ OP 7
TM R f o r P A 4 O n l y
IN T fo r P A 5 O n l y
S y s t em W ak e- up
( P A onl y )
R ead D a t a R egi s t er
PA 3
PF D
(P D 0 o r P W M 0 )
D
Q
CK
S
D
Q
CK
Q
S
C ont r o l B i t
PU
Da t a B u s
W r i t e C ont r o l R egi s t er
C h i p R es et
R ead C o n t r o l R e g i s t er
W r i t e D a t a R egi s t er
Da t a B i t
PA 0 ~ P A 2
PA 3 / PF D
PA 4 / T M R
PA 5 / I N T
PA 6 , P A7
P B 0/ A N 0~ P B 7/ A N 7
PC 0 ~ PC 5
PD 0 / P W M 0
PD 1 / P W M 1
(P D 1 o r P W M 1 )
Q
Input/output ports



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