HT46R22 datasheet(20/46 Pages) HOLTEK

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HT46R22/HT46C22

Rev. 1.10

October 2, 2002

2C BUS Serial Interface

2C BUS is implemented in the device. The I2C BUS is a

bidirectional 2-wire lines. The data line and clock line

are implement in SDA pin and SCL pin. The SDA and

SCL are NMOS open drain output pin. They must con-

nect a pull-high resistor respectively.

Using the I

2C BUS, the device has two ways to transfer

data. One is in slave transmit mode, the other is in slave

receive mode. There are four registers related to I

BUS; HADR([20H]), HCR([21H]), HSR([22H]),

HDR([23H]). The HADR register is the slave address

setting of the device, if the master sends the calling ad-

dress which match, it means that this device is selected.

The HCR is I

2C BUS control register which defines the

device enable or disable the I

2C BUS as a transmitter or

as a receiver. The HSR is I

2C BUS status register, it re-

sponds with the I

2C BUS status. The HDR is input/out-

put data register, data to transmit or receive must be via

the HDR register.

The I

2C BUS control register contains three bits. The

HEN bit define the enable or disable the I

2C BUS. If the

data wants transfer via I

2C BUS, this bit must be set.

The HTX bit defines whether the I

2C BUS is in transmit

or receive mode. If the device is as a transmitter, this bit

must be set to

²1². The TXAK defines the transmit ac-

knowledge signal, when the device received 8-bit data,

the device sends this bit to I

2C BUS at the 9th clock. If

the receiver wants to continue to receive the next data,

this bit must be reset to

²0² before receiving data.

The I

2C BUS status register contains 5 bits. The HCF bit

is reset to

²0² when one data byte is being transferred. If

one data transfer is completed, this bit is set to

²1². The

HASS bit is set

²1² when the address is match, and the

2C BUS interrupt request flag is set to ²1². If the inter-

rupt is enabled and the stack is not full, a subroutine call

to location 10H will occur. Writing data to the I

2C BUS

control register clears HAAS bit. If the address is not

match, this bit is reset to

²0². The HBB bit is set to re-

spond the I

2C BUS is busy. It mean that a START signal

is detected. This bit is reset to

²0² when the I2C BUS is

not busy. It means that a STOP signal is detected and

the I

2C BUS is free. The SRW bit defines the read/write

command bit, if the calling address is match. When

HAAS is set to

²1², the device check SRW bit to deter-

mine whether the device is working in transmit or re-

ceive mode. When SRW bit is set

²1², it means that the

master wants to read data from I

2C BUS, the slave de-

vice must write data to I

2C BUS, so the slave device is

working in transmit mode. When SRW is reset to

²0²,it

means that the master wants to write data to I

2C BUS,

the slave device must read data from the bus, so the

slave device is working in receive mode. The RXAK bit

is reset

²0² indicates an acknowledges signal has been

received. In the transmit mode, the transmitter checks

RXAK bit to know the receiver which wants to receive

the next data byte, so the transmitter continue to write

data to the I

2C BUS until the RXAK bit is set to ²1² and

the transmitter releases the SDA line, so that the master

can send the STOP signal to release the bus.

The HADR bit7-bit1 define the device slave address. At

the beginning of transfer, the master must select a de-

vice by sending the address of the slave device. The bit

0 is unused and is not defined. If the I

2C BUS receives a

start signal, all slave device notice the continuity of the

8-bit data. The front of 7 bits is slave address and the

first bit is MSB. If the address is match, the HAAS status

bit is set and generate an I

2C BUS interrupt. In the ISR,

the slave device must check the HAAS bit to know the

2C BUS interrupt comes from the slave address that

has match or completed one 8-bit data transfer. The last

bit of the 8-bit data is read/write command bit, it re-

sponds in SRW bit. The slave will check the SRW bit to

know if the master wants to transmit or receive data. The

device check SRW bit to know it is as a transmitter or re-

ceiver.

Bit7~Bit1

Bit0

Slave Address

HADR register

Note:

²¾² means undefined

The HDR register is the I

2C BUS input/output data regis-

ter. Before transmitting data, the HDR must write the

data which we want to transmit. Before receiving data,

the device must dummy read data from HDR. Transmit

or Receive data from I

2C BUS must be via the HDR reg-

ister. At the beginning of the transfer of the I

2C BUS, the

device must initial the bus, the following are the notes for

initialing the I

2C BUS:

1: Write the I

2C BUS address register (HADR) to define

its own slave address.

2: Set HEN bit of I

2C BUS control register (HCR) bit 0 to

enable the I

2C BUS.

Label

(HCR)

Bits

Function

HEN

To enable or disable I

2C BUS function

(0= disable; 1= enable)

Unused bit, read as

²0²

Unused bit, read as

²0²

HTX

To define the transmit or receive mode

(0= receive mode; 1= transmit)

TXAK

To enable or disable transmit acknowl-

edge (0= acknowledge; 1= don

¢t acknowl-

edge)

¾ 0~2 Unused bit, read as ²0²

HCR register

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