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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HCTL2000 датащи(PDF) 10 Page - Agilent(Hewlett-Packard) |
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HCTL2000 датащи(HTML) 10 Page - Agilent(Hewlett-Packard) |
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10 / 19 page  10 Inhibit Logic The Inhibit Logic Section samples the OE and SEL signals on the falling edge of the clock and, in response to certain conditions (see Figure 10 below), inhibits the position data latch. The RST signal asynchronously clears the inhibit logic, enabling the latch. A simplified logic diagram of the inhibit circuitry is illustrated in Figure 11. Bus Interface The bus interface section consists of a 16 to 8 line multiplexer and an 8-bit, three-state output buffer. The multiplexer allows independent access to the low and high bytes of the position data latch. The SEL and OE signals determine which byte is output and whether or not the output bus is in the high-Z state. In the case of the HCTL-2000 the data latch is only 12 bits wide and the upper four bits of the high byte are internally set to zero. Quadrature Decoder Output (HCTL-2020 Only) The quadrature decoder output section consists of count and up/ down outputs derived from the 4X decode logic of the HCTL- 2020. When the decoder has detected a count, a pulse, one- half clock cycle long, will be output on the CNTDCDR pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNTDCDR pulse, and held one clock cycle after the rising edge of the CNTDCDR pulse. These outputs are not affected by the inhibit logic. See Figures 5 and 12 for detailed timing. Cascade Output (HCTL- 2020 Only) The cascade output also consists of count and up/down outputs. When the HCTL-2020 internal counter overflows or underflows, a pulse, one-half clock cycle long, will be output on the CNTCAS pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNTCAS pulse, and held one clock cycle after the rising edge of the CNTCAS pulse. These outputs are not affected by the inhibit logic. See Figures 5 and 12 for detailed timing. Figure 11. Simplified Inhibit Logic. Inhibit Step SEL OE CLK Signal Action 1 L L 1 Set inhibit; read high byte 2 H L 1 Read low byte; starts reset 3 X H 0 Completes inhibit logic reset Figure 10. Two Byte Read Sequence. |
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