HCPL-260L datasheet(9/14 Pages) HP

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Package Characteristics

All Typicals at T A = 25˚C.

Parameter

Sym.

Package

Min.

Typ.

Max

Units

Test Conditions

Fig.

Note

Input-Output

II-O*

Single 8-Pin DIP

µA

45% RH, t = 5 s,

16, 17

Insulation

Single SO-8

VI-O = 3 kV DC, TA = 25˚C

Input-Output

VISO

8-Pin DIP, SO-8

2500

V rms

≤ 50%, t = 1 min,

16, 17

Momentary

TA = 25˚C

Withstand

Voltage**

Input-Output

RI-O

8-Pin, SO-8

1012

Ω

VI-O =500 V dc

1, 16, 19

Resistance

Input-Output

CI-O

8-Pin DIP, SO-8

0.6

f = 1 MHz, TA = 25˚C

1, 16, 19

Capacitance

Input-Input

II-I

Dual Channel

0.005

µA

≤ 45%, t = 5 s,

Insulation

VI-I = 500 V

Leakage

Current

Resistance

RI-I

Dual Channel

1011

Ω

(Input-Input)

Capacitance

CI-I

Dual 8-Pin Dip

0.03

f = 1 MHz

(Input-Input)

Dual SO-8

0.25

*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level

safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."

Notes:

1. Each channel.

2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not

exceed 20 mA.

3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not

exceed 15 mA.

4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.

5. Bypassing of the power supply line is required, with a 0.1

µF ceramic disc capacitor adjacent to each optocoupler as illustrated in

Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.

6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge

of the output pulse.

7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge

of the output pulse.

8. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test

conditions.

9. See test circuit for measurement details.

10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the

rising edge of the output pulse.

11. The tELH enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the

falling edge of the output pulse.

12. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state

(i.e., Vo > 2.0 V).

13. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state

(i.e., Vo < 0.8 V).

14. For sinusoidal voltages, (|dVCM | / dt)max =

πfCMVCM (p-p).

15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved

CMR performance. For single channel products only. See application information provided.

16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage

≥ 3000 V rms for one second (leakage

detection current limit, II-O

≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the

VDE 0884 Insulation Characteristics Table, if applicable.

18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage

≥ 6000 V rms for one second (leakage

detection current limit, II-O

≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the

VDE 0884 Insulation Characteristics Table, if applicable.

19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.

20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.

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