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CGS702V датащи(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали CGS702V
подробное описание детали  Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI
PDF  10 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

CGS702V датащи(HTML) 5 Page - National Semiconductor (TI)

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CGS702 AC Electrical Characteristics
over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C
Symbol
Parameter
VCC e 45V to 55V
Units
Notes
fIN e 25 MHz to 40 MHz
T e 0 Cto70 C
CL e Circuit 1 and 2
RL e Circuit 1 and 2
Min
Typ
Max
tRISE
Output Rise
CLK4
08V to 26V
ns
(Note 1)
CLK2
10V to VCC b 10V
20
CLK1
10V to VCC b 10V
tFALL
Output Fall
CLK4
26V to 08V
ns
(Note 1)
CLK2
VCC b 10V to 10V
20
CLK1
VCC b 10V to 10V
tSKEW
Maximum
a
to a Edges
CLK1
CLK1
500
Edge-to-Edge
a
to a Edges
CLK1
CLK4
1000
ps
(Note 2)
Output Skew
a
to a Edges
CLK2
CLK4
1500
tLOCK
Time to Lock the Output to the XTALIN Input
100
m
s
tCYCLE
Output Duty Cycle
CLK1 Outputs
49
51
CLK2 Output
49
51
%
(Note 3)
CLK4 Output
35
65
JLT
Output Jitter (Long Term)
300
ps
(Notes 4 5)
JCC
Output Jitter
CLK1
b
75
a
75
ps
(Notes 4 5 6)
(Cycle to Cycle)
CLK2
g
250
ps
(Notes 4 5 7)
CLK4
g
250
ps
(Notes 4 5 7)
FMIN
Minimum XTALIN Frequency
15
MHz
FMAX
Maximum XTALIN Frequency
43
MHz
Note 1
tRISE and tFALL parameters are measured at the pin of the device
Note 2
Skew is measured at 50% of VCC for CLK1 and CLK2 While it is measured at 14V for CLK4
Note 3
Output duty cycle is measured at VDD 2 for CLK1 and CLK2 While it is measured at 14V for CLK4
Note 4
Jitter parameter is characterized and is guaranteed by design only It measures the uncertainty of either the positive or the negative edge over 1000 cycles
It is also measured at output levels of VCC 2 Refer to Figure 2 for further explanation
Note 5
The GNDA pins of the 702 must be as free of noise as possible for minimum jitter Separate analog ground plane is recommended for the PCB
Also the VCCA pin requires extra filtering to further reduce noise Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin
Note 6
Cycle to Cycle Jitter is measured at VCC2
Note 7
Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25 C 5V measured
VCC2
TLF12386 – 4
Circuit 1 Test Circuit for CLK1 and CLK2
TLF12386 – 5
Circuit 2 Test Circuit for CLK4
5



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