LAN9250 datasheet(157/421 Pages) MICROCHIP

157 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 157

LAN9250

For more information on the EEPROM and EEPROM Loader, refer to Section 13.0, "I2C Master EEPROM Controller,"

on page 282.

11.10 FIFOs

The device contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and two internal inac-

cessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO).

11.10.1

TX/RX FIFOS

The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information, acting as a conduit

between the host bus interface (HBI) and the Host MAC. The sizes of these FIFOs are configurable via the Hardware

Configuration Register (HW_CFG) register to the ranges described in Table 11-10. Refer to Section 11.10.3, "FIFO

Memory Allocation Configuration" for additional information. The the RX and TX FIFOs related register definitions can

be found in section Section 11.14, "Host MAC & FIFO Interface Registers".

The TX and RX Data FIFOs have the base address of 20h and 00h respectively. However, each FIFO is also accessible

at seven additional contiguous memory locations, as can be seen in FIGURE 5-1: Register Address Map on page 30.

The Host may access the TX or RX Data FIFOs at any of these alias port locations, as they all function identically and

contain the same data. This alias port addressing is implemented to allow hosts to burst through sequential addresses.

For HBI access, the TX and RX Data FIFOs may also be accessed using FIFO Direct Selection mode. In this mode, the

address input is ignored and all read access are directed to the RX Data FIFO while all write accesses are directed to

the TX Data FIFO. See Section 9.4.3.2, "FIFO Direct Select Access," on page 80 and Section 9.5.5.3, "FIFO Direct

Select Access," on page 102.

The TX and RX Status FIFOs can each be read from two register locations; the Status FIFO Port, and the Status FIFO

PEEK. The TX and RX Status FIFO Ports (48h and 40h respectively) will perform a destructive read, popping the data

from the TX or RX Status FIFO. The TX and RX Status FIFO PEEK register locations (4Ch and 44h respectively) allow

a non-destructive read of the top (oldest) location of the FIFOs.

Proper use of the The TX/RX Data and Status FIFOs, including the correct data formatting is described in detail in Sec-

tion 11.11, "TX Data Path Operation," on page 159 and Section 11.12, "RX Data Path Operation," on page 170.

11.10.2

MIL FIFOS

The MAC Interface Layer (MIL), within the Host MAC, contains a 2KB transmit and a 128 Byte receive FIFO which are

separate from the TX and RX FIFOs. These MIL FIFOs are not directly accessible from the HBI. The differentiation

between the TX/RX FIFOs and the TX/RX MIL FIFOs is that once the transmit or receive packets are in the MIL FIFOs,

the host no longer can control or access the TX or RX data. The MIL FIFOs are essentially the working buffers of the

Host MAC logic. In the case of reception, the data must be moved into the RX FIFOs before the host can access the

data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning

transmission.

As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the size of the frames

to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in addition to any TX data that may be

queued in the TX Data FIFO.

Conversely, as data is received, it is moved from the Host MAC to the RX MIL FIFO, and then into the RX Data FIFO.

When the RX Data FIFO fills up, the current or subsequent RX frames will be lost until room is made in the RX Data

FIFO. For each frame of data that is lost, the Host MAC RX Dropped Frames Counter Register (RX_DROP) is incre-

mented.

RX and TX MIL FIFO levels are not visible to the host processor and operate independent of the TX/RX FIFOs. FIFO

levels set for the TX/RX Data and Status FIFOs do not take into consideration the MIL FIFOs.

11.10.3

FIFO MEMORY ALLOCATION CONFIGURATION

TX and RX FIFO space is configurable through the Hardware Configuration Register (HW_CFG). The user must select

the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the Hardware Configuration Register (HW_CFG).

The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status

FIFO size is fixed at 512 Bytes (128 TX Status DWORDs). The TX Status FIFO length is subtracted from the total TX

FIFO size with the remainder being the TX Data FIFO Size. The minimum size of the TX FIFOs is 2KB (TX Data and

TX Status FIFOs combined). Note that TX Data FIFO space includes both commands and payload data.

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