LAN9250 datasheet(112/421 Pages) MICROCHIP

112 / 421 page

LAN9250

DS00001913A-page 112

 2015 Microchip Technology Inc.

16-BIT BURST READ

FIFOSEL is set high and address bit 1 is set to access the lower WORD of the FIFO, while address bits 4:2 start at 0.

Read data is driven on D[15:0] during RD active. Address bit 1 is then set to access the WORD of the FIFO as RD is

held active.

While RD is held active, address bits 4:2 are cycled from 0 through 7 to access the 8 DWORDs as address bit 1 is tog-

gled to access each WORD. Fresh data is supplied each time A[1] toggles. The FIFO is popped when A[2] toggles.

8-BIT READ

FIFOSEL is set high and address bits 1 and 0 are set to access the lower BYTE of the FIFO, while address bits 4:2 are

don’t care. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle repeats for

the remaining 3 BYTEs of the FIFO’s DWORD.

FIGURE 9-37:

INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 16-BIT BURST READ

FIGURE 9-38:

INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 8-BIT READ

3'b000,1'b0

RX FIFO 15:8

D[15:8]

A[4:1]

RX FIFO 31:24

RX FIFO 7:0

D[7:0]

RX FIFO 23:16

FIFOSEL

3'b000,1'b1

3'b001,1'b0

3'b111,1'b0

3'b111,1'b1

3'b001,1'b1

RX FIFO 15:8 RX FIFO 31:24

RX FIFO 7:0

RX FIFO 23:16

RX FIFO 15:8 RX FIFO 31:24

RX FIFO 7:0

RX FIFO 23:16

3'bXXX,2'b00

D[15:8]

A[4:0]

3'bXXX,2'b01

RX FIFO 7:0

D[7:0]

RX FIFO 15:8

FIFOSEL

3'bXXX,2'b10

3'bXXX,2'b11

RX FIFO 23:16

RX FIFO 31:24

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