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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9250 датащи(PDF) 111 Page - Microchip Technology |
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LAN9250 датащи(HTML) 111 Page - Microchip Technology |
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111 / 421 page  2015 Microchip Technology Inc. DS00001913A-page 111 LAN9250 9.5.6.4 FIFO Direct Select Access The figures in this section detail FIFO Direct Select (FIFOSEL) read and write cycles in indexed address mode for 16 and 8-bit modes. Additionally, FIFO Direct Select Burst reads are shown for 16, and 8-bit modes. FIFO Direct Select Burst mode supports up to 8 DWORDs of consecutive reads. FIFO Direct Select (FIFOSEL) read and write cycles do not required an index register write. 16-BIT READ FIFOSEL is set high and address bit 1 is set to access the lower WORD of the FIFO, while address bits 4:2 are don’t care. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the FIFO. 16-BIT WRITE FIFOSEL is set high and address bit 1 is set to access the lower WORD of the FIFO, while address bits 4:2 are don’t care. Data on D[15:0] is written on the trailing edge of WR. The cycle repeats for the upper WORD of the FIFO. FIGURE 9-35: INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 16-BIT READ FIGURE 9-36: INDEXED ADDRESSING FIFO DIRECT SELECT ACCESS - 16-BIT WRITE CS RD WR 3'bXXX,1'b0 RX FIFO 15:8 D[15:8] A[4:1] 3'bXXX,1'b1 RX FIFO 31:24 RX FIFO 7:0 D[7:0] RX FIFO 23:16 FIFOSEL CS RD WR 3'bXXX,1'b0 TX FIFO 15:8 D[15:8] A[4:1] 3'bXXX,1'b1 TX FIFO 31:24 TX FIFO 7:0 D[7:0] TX FIFO 23:16 FIFOSEL |
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