Engineering Bulletin

EB413/D

© Motorola, Inc., 1993, 2000

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Figure 4. External Reset Sequence

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

Notes:

INTERNAL

DATA BUS

07FE

07FE

07FE

07FE

07FF

NEW PC

1. Internal clock, internal address bus, and internal data bus are not available externally.

2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.

NEW

PCH

NEW PC

NEW

PCL

DUMMY

OP

CODE

RESET

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com