MIC4102 datasheet(20/28 Pages) MICROCHIP

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MIC4102

DS20005575A-page 20

 2016 Microchip Technology Inc.

FIGURE 6-6:

Turn-Off Current Paths.

The following circuit guidelines should be adhered to

for optimum circuit performance:

•The VDD and HB bypass capacitors must be

placed close to the supply and ground pins. It is

critical that the etch length between the high side

decoupling capacitor (CB) and the HB and HS

pins be minimized to reduce lead inductance.

• A ground plane should be used to minimize

parasitic inductance and impedance of the return

paths. The MIC4102 is capable of greater than 3A

peak currents. Any impedance between the

MIC4102, the decoupling capacitors, and the

external MOSFET will degrade the performance

of the driver.

• Trace out the high di/dt and dv/dt paths, as shown

in Figure 6-5 and Figure 6-6 to minimize the etch

length and loop area for these connections.

Minimizing these parameters decreases the

parasitic inductance and the radiated EMI

generated by fast rise and fall times.

A typical layout of a synchronous buck converter power

stage using the MIC4102 (Figure 6-7) is shown in

Figure 6-8.

FIGURE 6-7:

Typical Converter Power

Stage.

FIGURE 6-8:

Typical Layout of a

Synchronous Buck Converter Power Stage.

The circuit is configured as a synchronous buck power

stage. The high-side MOSFET drain connects to the

input supply voltage (drain) and the source connects to

the switching node. The low-side MOSFET drain

connects to the switching node and its source is

connected to ground. The buck converter output

inductor (not shown) would connect to the switching

node. The high-side drive trace, HO, is routed on top

of its return trace, HS, to minimize loop area and

parasitic inductance. The low-side drive trace, LO, is

routed over the ground plane and minimizes the

impedance of that current path. The decoupling

capacitors, CB and CVDD, are placed to minimize etch

length between the capacitors and their respective

pins. This close placement is necessary to efficiently

charge capacitor CB when the HS node is low. All

traces are 0.025” wide or greater to reduce impedance.

CIN is used to decouple the high current path through

the MOSFETs.

LEVEL

SHIFT

PWM

VDD

LOW-SIDE DRIVE TURN-OFF

CURRENT PATH

HIGH-SIDE DRIVE

TURN-OFF CURRENT PATH

CHARGE C

B THROUGH

INTERNAL DIODE WHEN

HS PIN IS LOW

LEVEL

SHIFT

PWM

VDD

HIGH-SIDE

FET

LOW-SIDE

FET

FF_

(SWITCH NODE)

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