SST38VF6401 datasheet(13/64 Pages) MICROCHIP

13 / 64 page

DS-20005015B

08/15

64 Mbit (x16) Advanced Multi-Purpose Flash Plus

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Not Recommended for New Designs

If a Program or Erase operation is attempted on a protected sector or block, the operation will abort.

After the device initiates an abort, the corresponding Write Operation Status Detection Bits will stay

active for approximately 200ns (program or erase) before the device returns to read mode.

For the status of these bits during a Write operation, see Table 4.

Data# Polling (DQ7)

When the SST38VF6401/6402/6403/6404 are in an internal Program operation, any attempt to read

DQ7 will produce the complement of true data. For a Program Buffer-to-Flash operation, DQ7 is the

complement of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Once the

Program operation is completed, DQ7 will produce valid data. Note that even though DQ7 may have valid

data immediately following the completion of an internal Write operation, the remaining data outputs may still be

invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1

µs.

During an internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase

operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is

valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 11 for Data# Polling timing diagram

and Figure 26 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce

alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal Program or Erase opera-

tion is completed, the DQ6 bit will stop toggling, and the device is then ready for the next operation. For

Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#)

pulse. DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector or Block.

If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check

whether a particular sector or block is being actively erased or erase-suspended. Table 4 shows

detailed bit status information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or

CE#) pulse of Write operation. See Figure 12 for Toggle Bit timing diagram and Figure 26 for a flow-

chart.

DQ1

If an operation aborts during a Write-to-Buffer or Program Buffer-to-Flash operation, DQ1 is set to ‘1’.

To reset DQ1 to ‘0’, issue the Write-to-Buffer Abort Reset command to exit the abort state. A power-off/

power-on cycle or a Hardware Reset (RST# = 0) will also clear DQ1.

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