DS00537A-page 2

© 1992 Microchip Technology Inc.

Serial EEPROM Endurance

Error correction circuits are design techniques com-

monly used by EEPROM manufacturers to increase

endurance by reducing the failure rate caused by single

bit failures. These circuits are transparent to the user.

One typical scheme is using 4 bits of error correction for

every 8 “real” bits (one byte). In this scheme, one bit

failure in the byte is correctable, while if two bits within

the byte fail, the byte is not correctable.

Another error correction scheme is to use one “parity” bit

for every “cell.” Here both EEPROM cells must fail to

result in a bit fail.

A key point to remember is that most failures occurring

at less than 2 million E/W cycles are due to the number

of defects per a given area (defect density dependent.)

Thus high EEPROM endurance reliability is achieved by

reducing the defect density failure rates, not by increas-

ing the number of intrinsic cycles in the cell’s operational

design.

FIGURE 1 - CMOS FLOATING GATE EEPROM CELL

Memory Cell Gate

Row Select Transistor

Inter-Level Dielectric

90 ANG Td Oxide

Source

Drain

Bit Line

Row

Select

Memory

Cell Gate

Common Source

Read

Write

Erase

Standby

0.0 volts

0.0 volts

0.0 volts

0.0 volts

0.0 volts

20.0 volts

20.0 volts

0.0 volts

18.0 volts

20.0 volts

0.0 volts

Float

1.6 volts

5.0 volts

5.0 volts

0.0 volts

Bit Line

Row Select Gate

Memory Cell Gate

Common Source

(Not to scale)

Poly-Silicon, Level 2

Poly-Silicon, Level 2

Poly-Silicon, Level 1

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