TH71221 datasheet(12/44 Pages) MELEXIS

12 / 44 page

TH71221

27 to 930MHz

FSK/FM/ASK Transceiver

39010 071221

Page 12 of 44

Data Sheet

Rev. 009

Nov/15

Crystal

frequency fRO

Frequency

resolution fR

counter

Operating

frequency fVCO

3.0000MHz

2.93kHz

1023

13107

38.437MHz

3.0000MHz

2.93kHz

1023

131071

384.372MHz

8.0000MHz

12.5kHz

640

35812

447.65MHz

8.0000MHz

25kHz

320

34746

868.65MHz

8.0000MHz

250kHz

3660

915.0MHz

3.1.5 Phase-Frequency Detector

The phase-frequency detector creates an error voltage proportional to the phase difference between the

reference signal fR and fN. The implementation of the phase detector is a phase-frequency type. That circuitry

is very useful because it decreases the acquisition time significantly. The gain of the phase detector can be

expressed as:

PD 

(7)

where ICP is the charge pump current which is set via register CPCUR. In the TH7122 design the VCO

frequency control characteristic is with negative polarity. This means the VCO frequency increases if the loop

filter output voltage decreases and vice versa. When an external varactor diode is added to the VCO tank,

the tuning characteristic can be changed between positive and negative depending on the particular varactor

diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity.

3.1.6 Lock Detector

In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection

circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4

shows an overview of the lock signal generation. The locked state and the unlock condition will be decided

on the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down

signals are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches

steady state, the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM

sets the number of counts which are necessary to set the lock detection signal LD. If an unlock condition

occurs, the counter CNT_LD will be reloaded and therefore its CARRY falls back.

Fig. 4:

Lock Detection Circuit

RESET LD

Control

Logic

CNT_LD

CARRY

LOAD

Down

PFD

LDTM [1 : 0]

LOCKMODE

FRO

ERTM [1 : 0]

CNT_ER

CARRY

LOAD

MUX

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