VDP3108 datasheet(30/61 Pages) MICRONAS

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VDP 3108

ADVANCE INFORMATION

MICRONAS INTERMETALL

Name

Default

Function

Mode

Number

of bits

I2C Sub

address

w v

PLL2/3 filter coefficients, refer to section ‘horizontal deflection’

PKP3

PKP2

PKI2

w/r d

horizontal drive control register

bit [5:0]

0..63

horizontal drive pulse duration in

µsec

bit [6]

0/1

disable/enable horizontal pll loops

bit [7]

0/1

1: gate HOUT off during flyback

bit [8]

bit [9]

0/1

enable/disable ultra black blanking

bit [10]

0/1

force/enable blanking after reset

bit [11]

0/1

enable/disable analog RGB clamping

bit [12]

0/1

disable/enable composite sync(ref.bit[15])

bit [13]

0/1

enable/disable vertical protection

bit [14]

0/1

bypass/active display clock skew

bit [15,12]

function of CSIO pin

composite sync signal output

25 Hz output (field1/field2 signal)

no interlace (field 2), output = 0

1 MHz h–drive clock

HDRV

EHPLL

EFLB

DUBL

EBL

DCRGB

DVPR

CSKEW

CSYNC

TEST REGISTER

w/r

Main Test Register

w/r

Front End, Luma1

w/r

Front End, Luma2

w/r

Front End, Luma3

w/r

Front End, Chroma1

w/r

Front End, Chroma2

w/r

Display 1

w/r

Display 2

w/r

Display 3

w/r

Display Processor Control

w/r

Deflection

w/r

Analog Backend

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