MIC2873YCS datasheet(13/24 Pages) MICREL

13 / 24 page

Micrel, Inc.

MIC2873

Timing is designed such that when communicating with a

device using a low cost on chip oscillator, the worst case

minimum and maximum conditions can be easily met

within the wide operating range of the oscillator. Using this

method guarantees that the device can always detect the

delay introduced by the communication master.

Idle States and Error Conditions

In shutdown mode, the MIC2873 is in a reset condition

with all functions off while consuming minimal power.

out of shutdown state. In idle mode, all register settings

persist and all MIC2873 functions continue in their current

state. Table 1 summarises the difference between the two

idle modes:

Table 1. Differences between Idle Modes

Mode

Shutdown

Idle

VDC

Low

High

ISUPPLY

(all functions off)

1μA

230μA

Default

Persist

Start-Up Time

1μs

100ns

Idle mode is entered automatically at the end of a

communication frame by holding DC high for ≥T

END, by

enabling the device by bringing DC high when in shutdown

mode, or when an error is detected by the single-wire

interface logic.

Shutdown mode can be entered at any time by pulling

down DC for ≥T

END, discarding any current communication

and resetting the internal registers. If a communication is

received before the shutdown period but after the TLAT

period, the communication is discarded. This state is also

used to create an internal error state to avoid erroneously

latching data where the communication process cannot be

serviced

in time. Additionally, each register has a

maximum value associated with it. If the number of bits

clocked in exceeds the maximum value for the register, the

data is assumed to be in error and the data is discarded.

TEND

SHUTDOWN

IDLE

TEND

TLAT

IDLE

TLAT

TEND

TLAT

< TEND - TLAT

IDLE

Figure 2. Abort, Shutdown, and Idle Timing Waveforms

Communication Details

The serial interface requires delimiters to indicate the start

of frame, data as a series of pulses, and end of frame

indicated by a lack of activity for longer than TLAT. The

start of frame is the first high to low transition of DC when

in idle mode. The first rising edge resets the internal data

counter to 0.

AUTOMATIC LATCH

AFTER TLAT EXPIRES

TOFF

TON

TLAT

1 COUNT

TON+TOFF<TLAT

START

END OF

FRAME

Figure 3. Data Word Pulse Timing

A pulse is delimited by the signal first going below VL and

then above VH within the latch timeout TLAT. During this

transition, minimum on (TON) and off (TOFF) periods are

observed to improve tolerance to glitches.

Each rising

edge increments the internal data register. Data is

automatically latched into internal shadow address or data

registers after an inactivity period of DC remaining high for

longer than TLAT.

To send register write commands, the address and data

are entered in series as two data words using the above

pattern, with the second word starting after the first latch

period has expired. After the second word is entered, the

IDLE command should be issued by leaving the DC pin

high for ≥T

END

to indicate the stop sequence of the

address/data words frame.

July 17, 2014

Revision 1.0

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