AT9933 datasheet(7/16 Pages) MICROCHIP

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DS20005597A-page 7

AT9933

3.0

DETAILED DESCRIPTION

3.1

Power Topology

The AT9933 is optimized to drive a Continuous

Conduction Mode (CCM) boost-buck DC/DC converter

topology commonly referred to as Ćuk converter.

(Refer to Typical Application Circuit.) This power

converter topology offers numerous advantages useful

for driving high-brightness light-emitting diodes (HB

LED). These advantages include step-up or step-down

voltage conversion ratio and low input and output

current ripple. The output load is decoupled from the

input voltage with a capacitor, making the driver

inherently failure-safe for the output load.

The AT9933 offers a simple and effective control

technique for a boost-buck LED driver. It uses two

Hysteretic mode controllers—one for the input and one

for the output. The outputs of these two hysteretic

comparators are ANDED and used to drive the external

FET. This control scheme gives accurate current

control and constant output current in the presence of

input voltage transients without the need for

complicated loop design.

3.2

Input Voltage Regulator

The AT9933 can be powered directly from its VIN pin

that can withstand a maximum voltage of up to 75V.

When a voltage is applied to the VIN pin, the AT9933

seeks to regulate a constant 7.5V (typical) at the VDD

pin. The regulator also has a built-in undervoltage

lockout which shuts off the IC when the voltage at the

VDD pin falls below the UVLO threshold.

The VDD pin must be bypassed by a low-ESR capacitor

(≥0.1 μF) to provide a low-impedance path for the high

frequency current of the output gate driver.

The input current drawn from the VIN pin is the sum of

the 1 mA current drawn by the internal circuit and the

current drawn by the gate driver, which in turn depends

on the switching frequency and the gate charge of the

external FET. Refer to Equation 3-1.

EQUATION 3-1:

IIN

1mA QG fS



In the above equation, fS is the switching frequency,

and QG is the gate charge of the external FET which

can be obtained from the data sheet of the FET.

3.3

Minimum Input Voltage at VIN Pin

The minimum input voltage at which the converter will

start and stop depends on the minimum voltage drop

required for the linear regulator. The internal linear

regulator will control the voltage at the VDD pin when

VIN is between 8V and 75V. However, when the VIN is

less than 8V, the converter will still function as long as

the VDD is greater than the undervoltage lockout. Thus,

under certain conditions, the converter will be able to

start at VIN voltages of less than 8V. The start/stop

voltages at the VIN pin can be determined using the

maximum voltage drop across the linear regulator as a

function of the current drawn. The data for ambient

temperatures 25ºC and 125ºC are shown in Figure 3-1

below:

3.5

3.0

2.5

2.0

1.5

1.0

0.5

IN (mA)

125OC

25OC

FIGURE 3-1:

Maximum Voltage Drop vs.

Input Current.

Assume an ambient temperature of 125°C. Provided

that the IC is driving a 15 nC gate charge FET at

300 kHz, the total input current is estimated to be

5.5 mA (using Equation 3-1). At this input current, the

maximum voltage drop from Figure 3-1 can be

approximately estimated to be VDROP = 2.7V. However,

before the IC starts switching, the current drawn will be

1 mA. At this current level, the voltage drop is

approximately VDROP1 = 0.5V. Thus, the start/stop VIN

voltages can be computed as shown in Equation 3-2

and Equation 3-3:

EQUATION 3-2:

VIN START

–

UVLOMAX VDROP1

6.95V 0.5V

7.45V

EQUATION 3-3:

VIN STOP

–

UVLOMAX UVLO VDROP

–

6.95V 0.5V

–2.7V

9.15V

Note:

Since the gate driver draws too much cur-

rent in this situation, VIN-START is less than

VIN-STOP. The control IC will oscillate

between on and off if the input voltage is

between the start and stop voltages. In

these circumstances, it is recommended

that the input voltage be kept higher than

VIN-STOP. The IC will operate normally if

the input voltage is kept higher than 9.2V.

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