HV9982 datasheet(9/22 Pages) MICROCHIP

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DS20005295B-page 9

HV9982

3.0

FUNCTIONAL DESCRIPTION

3.1

Power Topology

HV9982 is a three-channel, switch-mode converter

LED driver designed to control a continuous conduction

mode buck, boost or SEPIC converter in a constant fre-

quency mode. The IC includes an internal linear regu-

lator, which operates from input voltages 10V to 40V.

The IC can also be powered directly using the VDD

pins and bypassing the internal linear regulator. The IC

includes features typically required in LED drivers such

as open LED protection, output short circuit protection,

linear and PWM dimming, programmable input current

limiting, and accurate control of the LED current. A high

current gate drive output enables the controller to be

used in high power converters. The IC is ideally suited

for backlight application using either RGB or multi-

channel white LED configurations.

3.2

Power Supply to the IC (VIN, VDD,

VDD1-3)

HV9982 can be powered directly from its VIN pin which

withstands a voltage up to 40V. When a voltage is

applied at the VIN pin, the HV9982 tries to maintain a

constant 7.75V (typ) at the VDD pin. The regulator also

has a built in under-voltage lockout, which shuts off the

IC if the voltage at the VDD pin falls below the UVLO

threshold. By connecting this VDD pin to pins VDD1-3

of the other three channels, the internal regulator can

be used to power all three channels in the IC.

If the internal regulator is not utilized, an external power

supply (7.0-9.0V) can be used to power the IC. In this

case, the power supply is directly connected to the

VDD1-3 pins and the VIN pin is left unconnected.

All four VDD pins must by bypassed by a low ESR

capacitor (≥0.1 µF) to provide a low impedance path for

the high frequency current of the output gate driver.

These capacitors must be referenced to the individual

grounds for proper noise rejection (see 3.13 “Layout

Considerations”). Also, in all cases, the four VDD pins

must be connected together externally.

The input current drawn from the external power supply

(or VIN pin) is a sum of the 4.5 mA (max) current drawn

by all the internal circuitry and the current drawn by the

gate drivers (which in turn depends on the switching

frequency and the gate charge of the external FET).

In the above equation, fS is the switching frequency of

the converters and Qg1-3 are the gate charges of the

external FETs (which can be obtained from the FET

data sheets).

The EN pin is a TTL-compatible input used to disable

the IC. Pulling the EN pin to GND will shut down the IC

and reduce the quiescent current drawn by the IC to be

less than 500 μA. If the enable function is not required,

the EN pin can be connected to VDD.

3.3

Clock Input (CLK)

The switching frequency of the converters is set by

using a TTL-compatible square wave input at the CLK

pin. The switching frequencies of the three converters

will be 1/12TH the frequency of the external clock.

3.4

Current Sense (CS1-3)

The current sense input is used to sense the source

current of the switching FET. Each CS input of the

HV9982 includes a built-in, 100 ns (minimum) blanking

time to prevent spurious turn off due to the initial current

spike when the FET turns on.

The IC includes an internal, resistor-divider network,

which steps down the voltage at the COMP pins by a

factor of 13. This voltage is used as the reference for

the current sense comparators. Since the maximum

voltage of the COMP pin is (VDD – 1.0V), this voltage

determines the maximum reference current for the cur-

rent sense comparator, and thus the maximum inductor

current.

The current sense resistor, RCS, should be chosen so

that the input inductor current is kept below the satura-

tion current level of the input inductor. For discontinu-

ous conduction mode of operation, no slope

compensation is necessary. In this case, the current

sense resistor is chosen as:

where IIN,pk is the maximum desired peak input current.

For continuous conduction mode converters operating

in the constant frequency mode, slope compensation

becomes necessary to ensure stability of the peak cur-

rent mode controller, if the operating duty cycle is

greater than 0.5. This factor must also be accounted for

when determining RCS (see 3.5 “Slope Compensa-

tion”).

3.5

Slope Compensation

Choosing a slope compensation, which is one half of

the down slope of the inductor current, ensures that the

converter will be stable for all duty cycles.

Slope compensation in the HV9982 can be pro-

grammed by two external components, see Figure 3-1.

A resistor for VDD sets a current, which is almost con-

stant since the VDD voltage is much larger than the volt-

age at the CS pin. This current flows into the capacitor

and produces a ramp voltage across the capacitor. The

voltage at the CS pin is then the sum of the voltage

IIN 4.5mA Q

Qg2 Qg3 



+fs



RCS

VDD 1.0V

–

13 IIN pk





-----------------------------

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